THIN FILM TRANSISTOR, ORGANIC LIGHT-EMITTING DIODE DISPLAY INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF

• US 20160149052A1
• Filed: 05/14/2015
• Published: 05/26/2016
• Est. Priority Date: 11/25/2014
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Ahn, Ki Wan, YOON, Joo Sun
• Granted Patent: US 9,768,310 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78663 Amorphous silicon transistors
• CPC Class Codes: H01L 29/78672 Polycrystalline or microcrystalline silicon transistor
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

A TFT, OLED display including the same, and manufacturing method thereof are disclosed. In one aspect, the TFT includes a first gate electrode formed over a substrate and a first insulating layer formed over the substrate and the first gate electrode. A semiconductor layer is formed over the first insulating layer, the semiconductor layer at least partially overlapping the first gate electrode. A second insulating layer is formed over the first insulating layer and the semiconductor layer, the first and second insulating layers having a pair of connection holes formed therethrough. A second gate electrode is electrically connected to the first gate electrode via the connection holes, the connection holes respectively exposing portions of the first gate electrode. Source and drain electrodes are formed over a third insulating layer and electrically connected to the semiconductor layer via the contact holes, the contact holes respectively exposing portions of the semiconductor layer.

Claims

1. A thin film transistor (TFT) for a display device, comprising:

a substrate;

a first gate electrode formed over the substrate;

a first insulating layer formed over the substrate and the first gate electrode;

a semiconductor layer formed over the first insulating layer, wherein the semiconductor layer at least partially overlaps the first gate electrode;

a second insulating layer formed over the first insulating layer and the semiconductor layer, wherein the first and second insulating layers have a pair of connection holes formed therethrough;

a second gate electrode electrically connected to the first gate electrode via the connection holes, wherein the connection holes respectively expose portions of the first gate electrode;

a third insulating layer formed over the second gate electrode and the second insulating layer, wherein the second and third insulating layers have a pair of contact holes formed therethrough; and

source and drain electrodes formed over the third insulating layer and electrically connected to the semiconductor layer via the contact holes, wherein the contact holes respectively expose portions of the semiconductor layer.

2. The TFT of claim 1, wherein the second gate electrode includes i) a second horizontal gate electrode formed over the second insulating layer and at least partially overlapping the semiconductor layer and the first gate electrode and ii) a pair of second vertical gate electrodes respectively formed in the connection holes.

3. The TFT of claim 2, wherein the second vertical gate electrodes extend downwardly from different portions of the second horizontal gate electrode.

4. The TFT of claim 3, wherein the semiconductor layer is formed of polysilicon.

5. The TFT of claim 3, wherein the semiconductor layer includes i) a channel region including first and second ends opposing each other, the channel region at least partially overlapping the first gate electrode and the second horizontal gate electrode and ii) source and drain regions respectively formed at the first and second ends of the channel region, and wherein the first gate electrode, the second horizontal gate electrode, and the second vertical gate electrodes surround the channel region.

6. The TFT of claim 5, wherein the second vertical gate electrodes respectively contact the source and drain regions.

7. The TFT of claim 2, wherein the second vertical gate electrodes respectively contact the exposed portions of the first gate electrode.

8. The TFT of claim 2, further comprising a gate line configured to transmit a gate signal to the first gate electrode,

wherein the first gate electrode is electrically connected to an end of the gate line, and

wherein the second horizontal gate electrode has a substantially rectangular shape in a plan view.

9. The TFT of claim 2, further comprising:

a gate line configured to transmit a gate signal to the first gate electrode; and

an auxiliary gate line at least partially overlapping the gate line,

wherein the first gate electrode is electrically connected to an end of the gate line, and

wherein the second horizontal gate electrode is electrically connected to an end of the auxiliary gate line.

10. The TFT of claim 2, wherein the first and second vertical and horizontal gate electrodes are connected to each other to form a closed loop.

11. A thin film transistor (TFT), comprising:

a substrate;

a first gate electrode formed over the substrate;

a first insulating layer formed over the substrate and the first gate electrode;

a semiconductor layer formed over the first insulating layer, wherein the semiconductor layer at least partially overlaps the first gate electrode;

source and drain electrodes respectively contacting portions of the semiconductor layer and separated from each other;

a second insulating layer formed over the semiconductor layer and the source and drain electrodes, wherein the first and second insulating layers have a pair of connection holes formed therethrough;

a second gate electrode electrically connected to the first gate electrode via the connection holes, wherein the connection holes respectively expose portions of the first gate electrode; and

a third insulating layer formed over the second gate electrode and the second insulating layer.

12. The TFT of claim 11, wherein the second gate electrode includes i) a second horizontal gate electrode formed over the second insulating layer and at least partially overlapping the semiconductor layer and the first gate electrode and ii) a pair of second vertical gate electrodes respectively formed in the connection holes.

13. The TFT of claim 12, wherein the second vertical gate electrodes respectively extend downwardly from different portions of the second horizontal gate electrode.

14. The TFT of claim 13, wherein the semiconductor layer is formed of an amorphous silicon or oxide semiconductor material.

15. The TFT of claim 13, wherein the semiconductor layer includes i) a channel region including first and second ends opposing each other, the channel region at least partially overlapping the first gate electrode and the second horizontal gate electrode and ii) source and drain regions respectively formed at the first and second ends of the channel region, and wherein the first gate electrode, the second horizontal gate electrode, and the second vertical gate electrodes surround the channel region.

16. The TFT of claim 15, wherein the second vertical gate electrodes respectively contact the source and drain regions.

17. The TFT of claim 15, further comprising:

a source ohmic contact formed between the source electrode and the source region; and

a drain ohmic contact formed between the drain electrode and the drain region.

18. The TFT of claim 12, wherein the second vertical gate electrodes respectively contact the exposed portions of the first gate electrode.

19. An organic light-emitting diode (OLED) display, comprising:

a substrate;

a thin film transistor (TFT) formed over the substrate; and

an OLED connected to the TFT,

wherein the TFT includes;

a first gate electrode formed over the substrate;

a first insulating layer formed over the substrate and the first gate electrode;

a semiconductor layer formed over the first insulating layer, wherein the semiconductor layer at least partially overlaps the first gate electrode;

a second insulating layer formed over the first insulating layer and the semiconductor layer, wherein the first and second insulating layers have a pair of connection holes formed therethrough;

a second gate electrode electrically connected to the first gate electrode via the connection holes, wherein the connection holes respectively expose a portion of the first gate electrode, respectively;

a third insulating layer formed over the second gate electrode and the second insulating layer, wherein the second and third insulating layers have a pair of contact holes formed therethrough; and

source and drain electrodes formed over the third insulating layer and electrically connected to the semiconductor layer via the contact holes, wherein the contact holes expose the portion of the semiconductor layer.

20. The OLED display of claim 19, wherein the second gate electrode includes i) a second horizontal gate electrode formed over the second insulating layer and at least partially overlapping the semiconductor layer and the first gate electrode and ii) a pair of second vertical gate electrodes respectively formed in the connection holes.

21. The OLED display of claim 20, wherein the semiconductor layer includes i) a channel region including first and second ends opposing each other, the channel region at least partially overlapping the first gate electrode and the second horizontal gate electrode and ii) source and drain regions respectively formed at the first and second ends of the channel region, and wherein the first gate electrode, the second horizontal gate electrode, and the second vertical gate electrodes surround the channel region.

22. The OLED display of claim 21, wherein the second vertical gate electrodes respectively contact the source and drain regions.

23. A manufacturing method of a thin film transistor (TFT), comprising:

forming a first gate electrode over a substrate, wherein the first gate electrode has two ends;

forming a first insulating layer over the first gate electrode;

forming a semiconductor layer, having two ends, over the first insulating layer so as to at least partially overlap the first gate electrode;

forming a second insulating layer over the first insulating layer and the semiconductor layer, wherein the first and second insulating layers have a pair of connection holes formed therethrough, and wherein the connection holes respectively expose the ends of the first gate electrode;

forming a second gate electrode over the second insulating layer, wherein the second gate electrode is electrically connected to the first gate electrode via the connection holes;

forming a third insulating layer over the second gate electrode and the second insulating layer, wherein the second and third insulating layers have a pair of contact holes formed therethrough, and wherein the contact holes respectively expose the ends of the semiconductor layer;

forming source and drain electrodes over the third insulating layer, wherein the source and drain electrodes are electrically connected to the semiconductor layer via the contact holes.

24. The method of claim 23, wherein the second gate electrode includes i) a second horizontal gate electrode formed over the second insulating layer and at least partially overlapping the semiconductor layer and the first gate electrode and ii) a pair of second vertical gate electrodes respectively formed in the connection holes.

25. The method of claim 24, wherein the semiconductor layer includes i) a channel region including first and second ends opposing each other, the channel region at least partially overlapping the first gate electrode and the second horizontal gate electrode, and wherein the first gate electrode, the second horizontal gate electrode, and the second vertical gate electrodes surround the channel region.