MASTER-SLAVE MULTI-PHASE CHARGING
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Accused Products
Abstract
A multi-phase charging circuit comprises a device that can be configured for master mode operation or slave mode operation. In master mode operation, the device generates a control signal and a clock signal to control operation of a switching circuit for generating charging current. In slave mode operation, the device receives externally generated control and clock signals to control operation of its switching circuit.
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Citations
32 Claims
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1-12. -12. (canceled)
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13. A charging circuit comprising:
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a control terminal; a clock terminal; a high-side field effect transistor (FET) and a low-side FET; a PWM driver to drive the high-side FET and the low-side FET; feedback circuitry to generate a control signal; a clock module comprising a clock generator and a delay element, the clock module to generate a clock signal that is provided to the PWM driver; and a selection module to configure the charging circuit in a first configuration or a second configuration, wherein in the first configuration, the control signal is provided to the PWM driver and to the control terminal, and the clock signal is provided from an output of the clock generator, wherein in the second configuration, an externally generated control signal received on the control terminal is provided to the PWM driver, an externally generated clock signal received on the clock terminal is provided to the delay element, and the clock signal is provided from an output of the delay element. - View Dependent Claims (14, 15, 16, 17, 21, 22, 23, 24)
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18. A charging circuit comprising:
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a PWM driver for driving a high side FET and a low side FET; a delay element; a first input pin electrically connected to the PWM driver to provide an externally provided control signal received on the first input pin as a control signal to the PWM driver; and a second input pin electrically connected to the delay element to provide the delay element with an externally provided clock signal received on the second input pin, wherein the delay element delays the externally provided clock signal to produce a delayed clock signal which is provided as a clock signal to the PWM driver. - View Dependent Claims (19, 20, 25, 26, 27)
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28. A charging circuit comprising:
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means for driving a high side FET and a low side FET; means for delaying a clock signal, the means for delaying connected to the means for driving; means for receiving a control signal generated separately from the charging circuit, connected to the means for driving; and means for receiving a clock signal generated separately from the charging circuit, connected to the means for delaying. - View Dependent Claims (29, 30, 31, 32)
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Specification