NOC TIMING POWER ESTIMATING DEVICE AND METHOD THEREOF

• US 20160149780A1
• Filed: 12/30/2014
• Published: 05/26/2016
• Est. Priority Date: 11/24/2014
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Hsu, Ting-Shuo, LIOU, Jing-Jia, SHEN, Jih-Sheng, Lu, Juin-Ming
• Granted Patent: US 9,842,180 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: G06F 2115/02 System on chip [SoC] design
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A NoC timing power estimating method includes: estimating a plurality of transmission timing of a plurality of transmission units of at least a packet, the transmission timing indicating respective time points at which the transmission units enter/leave a plurality of passing elements of the NoC; based on the transmission timing of the transmission units, estimating respective circuit states and respective power states of the passing elements of the NoC, the circuit state indicating an operation state of the passing element and the power state being related to the circuit state; and based on the power states of the passing elements of the NoC, estimating power consumption of the NoC.

Claims

1. A network-on-chip (NoC) timing power estimating method, comprising:

estimating a plurality of transmission timings of a plurality of transmission units of at least a packet, the transmission timings indicating respective time points at which the transmission units enter/leave a plurality of traversed elements of the NoC;

estimating respective circuit states and respective power states of the traversed elements of the NoC according to the transmission timings of the transmission units, wherein the circuit state indicates an operation state of the traversed element, and the power state is related to the circuit state; and

estimating power consumption of the NoC according to the power states of the traversed elements of the NoC.

2. The timing power estimating method according to claim 1, wherein, the step of estimating the transmission timings of the transmission units comprises:

determining a routing path of the packet according to at least a packet parameter and a routing parameter of the NoC;

performing arbitration to determine which packet gains a channel usage right if a plurality of routing paths of a plurality of packets conflict;

calculating the transmission timings of the transmission units; and

updating the circuit states of the traversed elements, and calculating a release timing of the channel usage right, to obtain a usage timing at which another packet gains the channel usage right.

3. The timing power estimating method according to claim 2, wherein,

according to whether the routing parameter is a dynamic routing or a static routing, determining whether update of the circuit states of the traversed elements affects the routing path of the packet.

4. The timing power estimating method according to claim 2, wherein, the step of calculating the transmission timings of the transmission units comprises:

determining the release timing (t_{stage[i]release}) at which an i-th router stage[i]is is released by the packet, wherein “

i”

is a positive integer;

determining a buffer passing time (Δ

t_passBUFFER) required for one of the transmission units of the packet to pass through a buffer if no congestion;

determining, when the buffer is full, a buffer allowed write time (Δ

t_syncBUFFER) between when one of the transmission units of the packet is read from the buffer and when a next transmission unit of the transmission units of the packet is written to the buffer; and

determining whether a congestion occurs.

5. The timing power estimating method according to claim 4, wherein, the step of determining whether the congestion occurs comprises:

determining a sum of a first header entering time (t<sub>stage[i−

1]flit[0]</sub>) at which a header transmission unit flit[0] of the packet enters an (i−

1)-th router stage[i−

1] plus the buffer passing time (Δ

t_passBUFFER) required for the header transmission unit flit[0] to pass through the buffer; and

comparing the sum with the release timing (t_{stage[i]release}) at which the i-th router stage[i] is released, to determine whether the congestion occurs.

6. The timing power estimating method according to claim 5, wherein, in a single-cycle router architecture,

if the congestion occurs, it is determined that a second header entering time (t_{stage[i]flit[0]}) at which the header transmission unit flit[0] enters the i-th router stage[i] is equivalent to a sum of the release timing (t_{stage[i]release}) at which the i-th router stage[i] is released plus a clock cycle;

if the congestion does not occur, it is determined that the second header entering time (t_{stage[i]flit[0]}) at which the header transmission unit flit[0] enters the i-th router stage[i] is equivalent to the first header entering time (t<sub>stage[i−

1]flit[0]</sub>) at which the header transmission unit flit[0] enters the (i−

1)-th router stage[i−

1] plus the buffer passing time (Δ

t_passFIFO) required for the header transmission unit flit[0] to pass through the buffer.

7. The timing power estimating method according to claim 6, wherein, in the single-cycle router architecture,

a j-th transmission unit entering time (t_{stage[i]flit[j]}) at which a j-th transmission unit flit[j] of the packet enters the i-th router stage[i] satisfies following conditions, wherein “

j”

is a positive integer;

the j-th transmission unit entering time (t_{stage[i]flit[j]}) is equivalent to a sum of a (j−

1)-th transmission unit entering time (t_{stage[i]flit[j-1]}) at which a (j−

1)-th transmission unit (flit[j−

1]) of the packet enters the i-th router stage[i] plus k clock cycles clk_stage[i] of the i-th router stage[i], wherein “

k”

is a positive integer;

the j-th transmission unit entering time (t_{stage[i]flit[j]}) at which the j-th transmission unit flit[j] of the packet enters the i-th router stage[i] is greater than a sum of a time (t<sub>stage[i−

1]flit[j]</sub>) at which the j-th transmission unit flit[j] enters the (i−

1)-th router stage[i−

1] plus the buffer passing time (Δ

t_passFIFO) required for the j-th transmission unit flit[j] to pass through the buffer; and

if the buffer having a depth of “

d”

is full, it is determined that the j-th transmission unit time (t_{stage[i]flit[j]}) at which the j-th transmission unit flit[j] enters the i-th router stage[i] is greater than a sum of a time (t_{stage[i+1]flit[j-d-1]}) at which a (j-d−

1)-th transmission unit flit[j-d−

1] enters an (i+1)-th router stage[i+1] plus the buffer allowed write time (Δ

t_synFIFO) at which the (j−

1)-th transmission unit flit[j−

1] is allowed to be written to the buffer, wherein “

d”

is a positive integer.

8. The timing power estimating method according to claim 5, wherein, in a 2-stage router architecture,

if the congestion occurs, it is determined that a second header entering time (t_{stage[i]flit[0]}) at which the header transmission unit flit[0] enters the i-th router stage[i] is equivalent to a sum of the release timing (t_{stage[i]release}) at which the i-th router stage[i] is released plus a clock cycle;

and

if the congestion does not occur, it is determined that the second header entering time (t_{stage[i]flit[0]}) at which the header transmission unit flit[0] enters the i-th router stage[i]is equivalent to a sum of the first header entering time (t<sub>stage[i−

1]flit[0]</sub>) at which the header transmission unit flit[0] enters the (i−

1)-th router stage[i−

1] plus the buffer passing time (Δ

t_passFIFO) required for the header transmission unit flit[0] to pass through the buffer and further plus the clock cycle.

9. The timing power estimating method according to claim 8, wherein, in the 2-stage router architecture,

a j-th transmission unit entering time (t_{stage[i]flit[j]}) at which a j-th transmission unit flit[j] of the packet enters the i-th router stage[i] satisfies following conditions, wherein “

j”

is a positive integer;

the j-th transmission unit entering time (t_{stage[i]flit[j]}) is equivalent to a (j−

1)-th transmission unit entering time (t_{stage[i]flit[j-1]}) at which a (j−

1)-th transmission unit (flit[j−

1]) of the packet enters the i-th router stage[i] plus k clock cycles clk_stage[i] of the i-th router stage[i], wherein “

k”

is a positive integer;

the j-th transmission unit entering time (t_{stage[i]flit[j]}) at which the j-th transmission unit flit[j] of the packet enters the i-th router stage[i] is greater than a sum of a time (t<sub>stage[i−

1]flit[j]</sub>) at which the j-th transmission unit flit[j] enters the (i−

1)-th router stage[i−

1] plus the buffer passing time (Δ

t_passFIFO) required for the j-th transmission unit flit[j] to pass through the buffer; and

if the buffer having a depth of “

d”

is full, it is determined that the j-th transmission unit time (t_{stage[i]flit[j]}) at which the j-th transmission unit flit[j] enters the i-th router stage[i] is greater than a sum of a time (t_{stage[i+1]flit[j-d-1]}) at which a (j-d−

2)-th transmission unit flit[j-d−

2] enters an (i+1)-th router stage[i+1] plus the buffer allowed write time (Δ

t_synFIFO) at which the (j−

1)-th transmission unit flit[j−

1] is allowed to be written to the buffer, wherein “

d”

is a positive integer.

10. The timing power estimating method according to claim 1, wherein, the step of estimating the circuit states and the power states of the traversed elements of the NoC comprises:

if one of the traversed elements is a buffer, determining a power state of the traversed element according to whether the buffer is written and whether the buffer is read;

or

if one of the traversed elements is the buffer, determining the power state of the traversed element according to whether the buffer is written, whether the buffer is read and a queue number in the buffer;

or

if one of the traversed elements is a router, determining the power state of the traversed element according to a write number and a read number of the router;

or

if one of the traversed elements is the router, determining the power state of the traversed element according to whether respective receive port of the router is written and whether respective transmit port of the router is read.

11. The timing power estimating method according to claim 1, wherein, the step of estimating the power consumption of the NoC comprises:

using a power model look-up-table to obtain respective power consumption of the traversed elements based on the power states of the traversed elements, and summing up the power consumption to estimate the power consumption of the NoC;

or

using an equation to obtain respective power consumption of the traversed elements based on the power states of the traversed elements, and summing up the power consumption to estimate the power consumption of the NoC.

12. A network-on-chip (NoC) timing power estimating device, comprising:

a transmission timing calculation unit for estimating a plurality of transmission timings of a plurality of transmission units of at least a packet, the transmission timings indicating respective time points at which the transmission units enter/leave a plurality of traversed elements of the NoC;

an element power state calculation unit for estimating respective circuit states and respective power states of the traversed elements of the NoC according to the transmission timings of the transmission units, wherein the circuit state indicates an operation state of the traversed element, and the power state is related to the circuit state; and

a power estimating unit for estimating power consumption of the NoC according to the power states of the traversed elements of the NoC.

13. The timing power estimating device according to claim 12, wherein:

the transmission timing calculation unit determines a routing path of the packet according to at least a packet parameter, and a routing parameter of the NoC;

if a plurality of routing paths of a plurality of packets conflict, the transmission timing calculation unit performs arbitration to determine which the packet gains a channel usage right;

the transmission timing calculation unit calculates the transmission timings of the transmission units; and

the transmission timing calculation unit updates the circuit states of the traversed element and calculates a release timing of the channel usage right, to obtain a usage timing at which another packet gains the channel usage right.

14. The timing power estimating device according to claim 13, wherein,

the transmission timing calculation unit determines whether update of the circuit states of the traversed elements affects the routing path of the packet according to whether the routing parameter is a dynamic routing or a static routing.

15. The timing power estimating device according to claim 13, wherein:

the transmission timing calculation unit calculates the release timing (t_{stage[i]release}) at which a i-th router stage[i] is released by the packet, wherein “

i”

is a positive integer;

the transmission timing calculation unit determines an buffer passing time (Δ

t_passBUFFER) required for one of the transmission units of the packet to pass through a buffer if no congestion;

the transmission timing calculation unit determines, when the buffer is full, an buffer allowed write time (Δ

t_syncBUFFER) between when one of the transmission units of the packet is read from the buffer and when a next transmission unit of the transmission units of the packet is written to the buffer; and

the transmission timing calculation unit determines whether a congestion occurs.

16. The timing power estimating device according to claim 15, wherein:

the transmission timing calculation unit calculates a sum of a first header entering time (t<sub>stage[i−

1]flit[0]</sub>) at which a header transmission unit flit[0] of the packet enters an (i−

1)-th router stage[i−

1] and the buffer passing time (Δ

t_passBUFFER) required for the header transmission unit flit[0] to pass through the buffer; and

the transmission timing calculation unit compares the sum with the release timing (t_{stage[i]release}) at which the i-th router stage[i] is released to determine whether the congestion occurs.

17. The timing power estimating device according to claim 16, wherein, in a single-cycle router architecture,

if the congestion occurs, the transmission timing calculation unit determines that a second header entering time (t_{stage[i]flit[0]}) at which the header transmission unit flit[0] enters the i-th router stage[i] is equivalent to a sum of the release timing (t_{stage[i]release}) at which the i-th router stage[i] is released plus a clock cycle;

if the congestion does not occur, the transmission timing calculation unit determines that the second header entering time (t_{stage[i]flit[0]}) at which the header transmission unit flit[0] enters the i-th router stage[i] is equivalent to a sum of the first header entering time (t<sub>stage[i−

1]flit[0]</sub>) at which the header transmission unit flit[0] enters the (i−

1)-th router stage[i−

1] plus the buffer passing time (Δ

t_passFIFO) required for the header transmission unit flit[0] to pass through the buffer.

18. The timing power estimating device according to claim 17, wherein, in the single-cycle router architecture,

the transmission timing calculation unit determines that a j-th transmission unit entering time (t stage[i]flit[j]) at which a j-th transmission unit flit[j] of the packet enters the i-th router stage[i] satisfies following conditions, wherein “

j”

is a positive integer;

the j-th transmission unit entering time (t_{stage[i]flit[j]}) is equivalent to a sum of a (j−

1)-th transmission unit entering time (t_{stage[i]flit[j-1]}) at which a (j−

1)-th transmission unit (flit[j−

1]) of the packet enters the i-th router stage[i] plus k clock cycles clk_stage[i] of the i-th router stage[i], wherein “

k”

is a positive integer;

the j-th transmission unit entering time (t_{stage[i]flit[j]}) at which the j-th transmission unit flit[j] of the packet enters the i-th router stage[i] is greater than a sum of a time (t<sub>stage[i−

1]flit[j]</sub>) at which the j-th transmission unit flit[j] enters the (i−

1)-th router stage[i−

1] plus the buffer passing time (Δ

t_passBUFFER) required for the j-th transmission unit flit[j] to pass through the buffer; and

if the buffer having a depth of “

d”

is full, the j-th transmission unit time (t_{stage[i]flit[j]}) at which the j-th transmission unit flit[j] enters the i-th router stage[i] is greater than a sum of a time (t_{stage[i+1]flit[j-d-1]}) at which a (j-d−

1)-th transmission unit flit[j-d−

1] enters a (i+1)-th router stage[i+1] plus the buffer allowed write time (Δ

t_synFIFO) at which the (j−

1)-th transmission unit flit[j−

1] is allowed to be written to the buffer, wherein “

d”

is a positive integer.

19. The timing power estimating device according to claim 16, wherein, in a 2-stage router architecture,

if the congestion occurs, it is determined that a second header entering time (t_{stage[i]flit[0]}) at which the header transmission unit flit[0] enters the i-th router stage[i] is equivalent to a sum of the release timing (t_{stage[i]release}) at which the i-th router stage[i] is released plus a clock cycle;

if the congestion does not occur, the second header entering time (t_{stage[i]flit[0]}) at which the header transmission unit flit[0] enters the i-th router stage[i] is equivalent to a sum of the first header entering time (t<sub>stage[i−

1]flit[0]</sub>) at which the header transmission unit flit[0] enters the (i−

1)-th router stage[i−

1] plus the buffer passing time (Δ

t_passFIFO) required for the header transmission unit flit[0] to pass through the buffer and further plus the clock cycle.

20. The timing power estimating device according to claim 19, wherein, in the 2-stage router architecture,

a j-th transmission unit entering time (t_{stage[i]flit[j]}) at which a j-th transmission unit flit[j] of the packet enters the i-th router stage[i] satisfies following conditions, wherein “

j”

is a positive integer;

the j-th transmission unit entering time (t_{stage[i]flit[j]}) is equivalent to a sum of a (j−

1)-th transmission unit entering time (tstage[i]flit[j−

1]) at which a (j−

1)-th transmission unit (flit[j−

1]) of the packet enters the i-th router stage[i] plus k clock cycles clk_stage[i] of the i-th router stage[i], wherein “

k”

is a positive integer;

the j-th transmission unit entering time (t_{stage[i]flit[j]}) at which the j-th transmission unit flit[j] of the packet enters the i-th router stage[i] is greater than a sum of a time (t<sub>stage[i−

1]flit[j]</sub>) at which the j-th transmission unit flit[j] enters the (i−

1)-th router stage[i−

1] plus the buffer passing time (Δ

t_passBUFFER) required for the j-th transmission unit flit[j] to pass through the buffer; and

if the buffer having a depth of “

d”

is full, the j-th transmission unit time (t_{stage[i]flit[j]}) at which the j-th transmission unit flit[j] enters the i-th router stage[i] is greater than a sum of a time (t_{stage[i+1]flit[j-d-1]}) at which a (j-d−

2)-th transmission unit flit[j-d−

2] enters an (i+1)-th router stage[i+1] plus the buffer allowed write time (Δ

t_synFIFO) at which the (j−

1)-th transmission unit flit[j−

1] is allowed to be written to the buffer, wherein “

d”

is a positive integer.

21. The timing power estimating device according to claim 12, wherein:

if one of the traversed elements is a buffer, the element power state calculation unit determines a power state of the traversed element according to whether the buffer is written and whether the buffer is read;

or

if one of the traversed elements is the buffer, the element power state calculation unit determines the power state of the traversed element according to whether the buffer is written, whether the buffer is read and a queue number in the buffer;

or

if one of the traversed elements is a router, the element power state calculation unit determines the power state of the traversed element according to a write number and a read number of the router;

or

if one of the traversed elements is the router, the element power state calculation unit determines the power state of the traversed element according to whether respective receive port of the router is written and whether respective transmit port of the router is read.

22. The timing power estimating device according to claim 12, wherein:

the power estimating unit uses a power model look-up-table to obtain respective power consumption of the traversed elements based on the power states of the traversed elements and to sum up the power consumption to estimate the power consumption of the NoC;

or

the power estimating unit uses an equation to obtain respective power consumption of the traversed elements based on the power states of the traversed elements, and to sum up the power consumption to estimate the power consumption of the NoC.

23. The timing power estimating device according to claim 12, wherein, the transmission timing calculation unit, the element power state calculation unit, and the power estimating unit are realized by at least a processor.

24. The timing power estimating device according to claim 13, wherein the transmission timing calculation unit, the element power state calculation unit, and the power estimating unit are realized by at least an integrated circuit.