MULTIPLE ENDIANNESS COMPATIBILITY
First Claim
1. A method, comprising:
- receiving a plurality of bytes in a particular endianness format; and
responsive to the particular endianness format being a first endianness format;
reordering bits of each byte of the plurality of bytes on a bytewise basis;
storing the reordered plurality of bytes in an array of memory cells; and
adjusting a shift direction associated with performing a number of operations on the plurality of bytes stored in the array; and
responsive to the particular endianness format being a second endianness format, storing the plurality of bytes in the array without reordering bits of the plurality of bytes.
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Accused Products
Abstract
Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of bytes and determining a particular endianness format of the plurality of bytes. The method can include, responsive to determining the particular endianness format is a first endianness format, reordering bits of each byte of the plurality of bytes on a bytewise basis, storing the reordered plurality of bytes in an array of memory cells, and adjusting a shift direction associated with performing a number of operations on the plurality of bytes stored in the array. The method can include, responsive to determining the particular endianness format is a second endianness format, storing the plurality of bytes in the array without reordering bits of the plurality of bytes.
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Citations
33 Claims
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1. A method, comprising:
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receiving a plurality of bytes in a particular endianness format; and responsive to the particular endianness format being a first endianness format; reordering bits of each byte of the plurality of bytes on a bytewise basis; storing the reordered plurality of bytes in an array of memory cells; and adjusting a shift direction associated with performing a number of operations on the plurality of bytes stored in the array; and responsive to the particular endianness format being a second endianness format, storing the plurality of bytes in the array without reordering bits of the plurality of bytes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method, comprising:
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determining a status of a flag indicating an endianness of a plurality of bytes; in response to a flag being set, indicating the plurality of bytes is received in a first endianness format; changing a direction of shifting operations performed in an array of memory cells; on a bytewise basis, reversing, via a controller, an order of bits of the plurality of bytes stored in a group of memory cells; reversing an order of addresses on a bytewise basis; and providing the bits with the reversed order and the corresponding addresses with reversed order to a host; and in response to the flag not being set based on the plurality of bytes being received in a second endianness format; providing the bits of the plurality of bytes stored in the group of memory cells to the host. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. An apparatus comprising:
a controller coupled to an array of memory cells, wherein the controller is configured to; receive bits of a plurality of bytes, wherein; when the bits are in a first endian format a flag is set; and when the bits are in a second endian format the flag is not set; reorder the received bits when the flag is set from the first endian format to the second endian format by reversing the bits in each byte as each byte is received; and reverse an order of the addresses associated with the plurality of bytes when the flag is set. - View Dependent Claims (27, 28, 29, 30)
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31. An apparatus comprising:
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a controller comprising an engine and configured to; receive bits of bytes in a particular endianness format; determine whether a flag is set, wherein the flag is set when the particular endianness format is a first endianness format and the flag is not set when the particular endianness format is a second endianness format; when the flag is set; cause the engine to reorder the received bits in the bytewise little endian format to a bit-sequential little endian format by reversing the bits bytewise; reverse an order of addresses associated with the bits; and store the bits in a group of memory cells of an array; and an array of memory cells comprising the group of memory cells and configured to perform a number of shift operations on the bits. - View Dependent Claims (32, 33)
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Specification