METHOD OF ANALOG FRONT END OPTIMIZATION IN PRESENCE OF CIRCUIT NONLINEARITY

• US 20160154923A1
• Filed: 10/30/2015
• Published: 06/02/2016
• Est. Priority Date: 12/02/2014
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Malhotra, Gaurav
• Granted Patent: US 9,858,381 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2111/08 Probabilistic or stochastic CAD
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method for manufacturing a serial link including a channel and a receiver, the link including linear time-invariant elements, the receiver including a continuous-time linear equalizer (CTLE) including a nonlinear block, and a slicer having an input. The method includes: for each of a plurality of candidate CTLE configurations: calculating a first probability density function (PDF), corresponding to a first signal value, at the input of the nonlinear block, calculating a first PDF, corresponding to the first signal value, at the output of the nonlinear block; calculating a second PDF, corresponding to a second signal value, at the input of the nonlinear block, calculating a second PDF, corresponding to the second signal value, at the output of the nonlinear block; and calculating a bit error rate.

Claims

1. A method for manufacturing a serial link comprising a channel and a receiver, the link comprising a plurality of linear time-invariant blocks, the receiver comprising a continuous-time linear equalizer (CTLE) comprising a nonlinear block having an input and an output, and a slicer having an input, the method comprising:

for each of a plurality of candidate CTLE configurations of the CTLE;

calculating a first probability density function (PDF), corresponding to a first signal value, at the input of the nonlinear block,

calculating a first PDF, corresponding to the first signal value, at the output of the nonlinear block from the first PDF at the input of the nonlinear block;

calculating a second PDF, corresponding to a second signal value, at the input of the nonlinear block,

calculating a second PDF, corresponding to the second signal value, at the output of the nonlinear block from the second PDF at the input of the nonlinear block;

calculating a bit error rate, from;

the first PDF at the output of the nonlinear block; and

the second PDF at the output of the nonlinear block;

selecting a configuration, from among the candidate CTLE configurations, satisfying a criterion; and

fabricating the CTLE with the selected configuration.

2. The method of claim 1, wherein the selecting of the configuration from among the plurality of candidate CTLE configurations satisfying the criterion comprises selecting a configuration from among the plurality of candidate CTLE configurations for which the calculated bit error rate is least.

3. The method of claim 1, wherein the calculating of the first PDF at the input of the nonlinear block comprises:

calculating a first noise contribution at the input of the nonlinear block;

calculating a second noise contribution at the input of the nonlinear block, and

calculating a convolution of;

a PDF of a signal contribution for a first signal value;

a PDF of the first noise contribution; and

a PDF of the second noise contribution.

4. The method of claim 3, wherein the calculating of the first noise contribution at the input of the nonlinear block comprises:

calculating the convolution of;

an autocorrelation function of a noise contribution at the input of a linear time-invariant block, of the plurality of linear time-invariant blocks, connected to the nonlinear block and

an impulse response of the linear time-invariant block.

5. The method of claim 1, wherein the calculating of the bit error rate comprises calculating the sum of:

the integral, from negative infinity to zero, of the first PDF at the output of the nonlinear block and

the integral, from zero to positive infinity, of the second PDF at the output of the nonlinear block.

6. The method of claim 1, wherein the calculating of the bit error rate comprises calculating a first PDF at the input of the slicer, the calculating of the first PDF at the input of the slicer comprising:

calculating a convolution of;

the first PDF at the output of the nonlinear block; and

a PDF of a decision feedback equalizer (DFE) output.

7. The method of claim 6, further comprising calculating the PDF of the DFE output, the calculating of the PDF of the DFE output comprising calculating a convolution of a plurality of tap PDFs, each tap PDF being the product of a DFE tap weight and a PDF of a data signal.

8. The method of claim 7, wherein the calculating of the bit error rate further comprises calculating the sum of:

the integral, from negative infinity to zero, of the first PDF at the input of the slicer.

9. The method of claim 1, wherein a first candidate CTLE configuration of the plurality of candidate CTLE configurations has a zero at a first frequency and a second candidate CTLE configuration of the plurality of candidate CTLE configurations has a zero at a second frequency, the second frequency being at least 10% greater than the first frequency.

10. The method of claim 1, wherein a first candidate CTLE configuration of the plurality of candidate CTLE configurations has a pole at a first frequency and a second candidate CTLE configuration of the plurality of candidate CTLE configurations has a pole at a second frequency, the second frequency being at least 10% greater than the first frequency.

11. A system for manufacturing a serial data link comprising a channel and a receiver, the link comprising linear time-invariant elements, the receiver having a continuous-time linear equalizer (CTLE) comprising a nonlinear block and a slicer having an input, the system comprising:

a processing unit; and

an integrated circuit fabrication equipment,

the processing unit being configured to;

for each of a plurality of candidate CTLE configurations of the CTLE;

calculate a first probability density function (PDF), corresponding to a first signal value, at the input of the nonlinear block,

calculate a first PDF, corresponding to the first signal value, at the output of the nonlinear block from the first PDF at the input of the nonlinear block;

calculate a second PDF, corresponding to a second signal value, at the input of the nonlinear block,

calculate a second PDF, corresponding to the second signal value, at the output of the nonlinear block from the second PDF at the input of the nonlinear block;

calculate a bit error rate, from;

the first PDF at the output of the nonlinear block; and

the second PDF at the output of the nonlinear block;

select a configuration, from among the plurality of candidate CTLE configurations, satisfying a criterion; and

the integrated circuit fabrication equipment being capable of fabricating the CTLE with the selected CTLE configuration.

12. The system of claim 11, wherein the selecting of a configuration from among the plurality of candidate CTLE configurations satisfying a criterion comprises selecting a configuration from among the plurality of candidate CTLE configurations for which the calculated bit error rate is least.

13. The system of claim 11, wherein the calculating of the first PDF at the input of the nonlinear block comprises:

calculating a first noise contribution at the input of the nonlinear block;

calculating a second noise contribution at the input of the nonlinear block, and

calculating a convolution of;

a PDF of a signal contribution for a first signal value;

a PDF of the first noise contribution; and

a PDF of the second noise contribution.

14. The system of claim 13, wherein the calculating of the first noise contribution at the input of the nonlinear block comprises:

calculating the convolution of;

an autocorrelation function of a noise contribution at the input of a linear time-invariant block, of the plurality of linear time-invariant blocks, connected to the nonlinear block and

an impulse response of the linear time-invariant block.

15. The system of claim 11, wherein the calculating of the bit error rate comprises calculating the sum of

the integral, from negative infinity to zero, of the first PDF at the output of the nonlinear block and

the integral, from zero to positive infinity, of the second PDF at the output of the nonlinear block.

16. The system of claim 11, wherein the calculating of the bit error rate comprises calculating a first PDF at the input of the slicer, the calculating of the first PDF at the input of the slicer comprising:

calculating a convolution of;

the first PDF at the output of the nonlinear block; and

a PDF of a decision feedback equalizer (DFE) output.

17. The system of claim 16, wherein the calculating of the bit error rate further comprises calculating the PDF of the DFE output, the calculating of the PDF of the DFE output comprising calculating a convolution of a plurality of tap PDFs, each tap PDF being the product of a DFE tap weight and a PDF of a data signal.

18. The system of claim 17, wherein the calculating of the bit error rate further comprises calculating the sum of:

the integral, from negative infinity to zero, of the first PDF at the input of the slicer.

19. The system of claim 11, wherein a first candidate CTLE configuration of the plurality of candidate CTLE configurations has a zero at a first frequency and a second candidate CTLE configuration of the plurality of candidate CTLE configurations has a zero at a second frequency, the second frequency being at least 10% greater than the first frequency.

20. A system for fabricating a serial data link comprising a channel and a receiver, the link comprising linear time-invariant elements, the receiver having a continuous-time linear equalizer (CTLE) comprising a nonlinear block and a slicer having an input, the system comprising:

means for;

for each of a plurality of candidate CTLE configurations;

calculating a first probability density function (PDF), corresponding to a first signal value, at the input of the nonlinear block,

calculating a first probability density function (PDF), corresponding to the first signal value, at the output of the nonlinear block;

calculating a second probability density function (PDF), corresponding to a second signal value, at the input of the nonlinear block,

calculating a second probability density function (PDF), corresponding to the second signal value, at the output of the nonlinear block;

calculating a bit error rate, from;

the first probability density function (PDF) at the output of the nonlinear block; and

the second probability density function (PDF) at the output of the nonlinear block;

means for selecting a configuration, from among the configurations, satisfying a criterion; and

means for fabricating a CTLE with the selected configuration.