Ferroelectric Field Effect Transistors, Pluralities Of Ferroelectric Field Effect Transistors Arrayed In Row Lines And Column Lines, And Methods Of Forming A Plurality Of Ferroelectric Field Effect Transistors

• US 20160155855A1
• Filed: 01/25/2016
• Published: 06/02/2016
• Est. Priority Date: 04/24/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ramaswamy, Durai Vishak Nirmal, Prall, Kirk D.
• Granted Patent: US 9,761,715 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6684 with a ferroelectric gate insulator
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 51/30 characterised by the memory core region

Abstract

A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. A gate construction of the transistor comprises inner dielectric extending along the channel top and laterally along the channel sidewalls. Inner conductive material is elevationally and laterally outward of the inner dielectric and extends along the channel top and laterally along the channel sidewalls. Outer ferroelectric material is elevationally outward of the inner conductive material and extends along the channel top. Outer conductive material is elevationally outward of the outer ferroelectric material and extends along the channel. Other constructions and methods are disclosed.

Claims

1. A ferroelectric field effect transistor, comprising:

a semiconductive channel comprising opposing sidewalls and an elevationally outermost top;

a source/drain region at opposite ends of the channel; and

a gate construction comprising;

inner dielectric extending along the channel top and laterally along the channel sidewalls;

inner conductive material elevationally and laterally outward of the inner dielectric and extending along the channel top and laterally along the channel sidewalls;

outer ferroelectric material elevationally outward of the inner conductive material and extending along the channel top; and

outer conductive material elevationally outward of the outer ferroelectric material and extending along the channel top.

2. The transistor of claim 1 wherein no portion of the outer ferroelectric material is laterally over any of the channel sidewalls.

3. The transistor of claim 1 wherein no portion of the outer conductive material is laterally over any of the channel sidewalls.

4. The transistor of claim 1 wherein the source/drain regions each have a maximum elevational thickness that is less than a maximum elevational thickness of the inner dielectric.

5. The transistor of claim 1 wherein the source/drain regions each have a maximum elevational thickness that is less than a maximum elevational thickness of the inner conductive material.

6. The transistor of claim 1 wherein the inner conductive material has a maximum elevational thickness that is greater than a minimum width of the channel taken orthogonally relative to a shortest straight-line distance between the source/drain regions.

7. The transistor of claim 1 wherein the inner conductive material has a maximum elevational thickness that is greater than length of the channel along a shortest straight-line distance between the source/drain regions.

8. The transistor of claim 1 wherein the inner conductive material and the inner dielectric have respective elevationally innermost surfaces that are not elevationally coincident.

9. The transistor of claim 1 wherein all of the outer conductive material, the outer ferroelectric material, the inner conductive material, and the inner dielectric have at least two laterally opposing vertical sidewalls elevationally outward of the channel that are laterally coincident relative one another.

10. The transistor of claim 1 wherein all of the outer conductive material, the outer ferroelectric material, and the inner conductive material have at least two pairs of two laterally opposing vertical sidewalls elevationally outward of the channel that are laterally coincident relative one another.

11. The transistor of claim 1 wherein the outer ferroelectric material and the inner conductive material have respective encircling perimeter edges in at least one respective horizontal cross section elevationally outward of the channel that are everywhere laterally coincident.

12. The transistor of claim 1 wherein the outer ferroelectric material and the outer conductive material have respective encircling perimeter edges in at least one respective horizontal cross section elevationally outward of the channel that are everywhere laterally coincident.

13. The transistor of claim 1 wherein the inner conductive material and the outer conductive material have respective encircling perimeter edges in at least one respective horizontal cross section elevationally outward of the channel that are everywhere laterally coincident.

14. The transistor of claim 13 wherein the outer ferroelectric material has an encircling perimeter edge in at least one horizontal cross section elevationally outward of the channel that is everywhere laterally coincident with said encircling perimeter edges of the inner and outer conductive materials.

15. An MFMIS transistor where F is along a horizontal channel surface and I is along a vertical channel surface.

16. The transistor of claim 15 wherein F is not along any vertical channel surface of the transistor.

17. The transistor of claim 15 wherein I is along two vertical channel surfaces of the transistor.

18. The transistor of claim 15 wherein total area of I that is over the channel of the transistor is greater than total area of F that is over the channel of the transistor.

19. A plurality of ferroelectric field effect transistors arrayed in row lines and column lines, comprising:

individual ferroelectric field effect transistors comprising;

a semiconductive channel comprising opposing sidewalls and an elevationally outermost top;

a source/drain region at opposite ends of the channel; and

a gate construction comprising;

inner dielectric extending along the channel top and laterally along the channel sidewalls;

inner conductive material elevationally and laterally outward of the inner dielectric and extending along the channel top and laterally along the channel sidewalls;

outer ferroelectric material elevationally outward of the inner conductive material and extending along the channel top;

outer conductive material elevationally outward of the outer ferroelectric material and extending along the channel top; and

at least one of the outer conductive material and the outer ferroelectric material being discontinuous along both of the row lines and the column lines between immediately adjacent transistors.

20. The transistors of claim 19 wherein both of the outer conductive material and the outer ferroelectric material are discontinuous along both of the row lines and the column lines between immediately adjacent transistors.

21. The transistors of claim 20 wherein the outer conductive material and the outer ferroelectric material have at least two pairs of two laterally opposing vertical sidewalls elevationally outward of the channel that are laterally coincident.

37. The transistor of claim 19 wherein no portion of the outer ferroelectric material is laterally over any of the channel sidewalls. (New):

The transistor of claim 19 wherein no portion of the outer conductive material is laterally over any of the channel sidewalls.

39. The transistor of claim 19 wherein the inner conductive material has a maximum elevational thickness that is greater than a minimum width of the channel taken orthogonally relative to a shortest straight-line distance between the source/drain regions.

40. The transistor of claim 19 wherein the inner conductive material has a maximum elevational thickness that is greater than length of the channel along a shortest straight-line distance between the source/drain regions.

41. The transistor of claim 19 wherein the inner conductive material and the inner dielectric have respective elevationally innermost surfaces that are not elevationally coincident.

22. A plurality of ferroelectric field effect transistors arrayed in row lines and column lines, comprising:

individual ferroelectric field effect transistors comprising;

a semiconductive channel comprising sidewalls and an elevationally outermost top;

a source/drain region at opposite ends of the channel; and

a gate construction comprising;

inner dielectric extending along the channel top and laterally along the channel sidewalls;

inner conductive material elevationally and laterally outward of the inner dielectric and extending along the channel top and laterally along the channel sidewalls;

outer ferroelectric material elevationally outward of the inner conductive material and extending along the channel top; and

outer conductive material elevationally outward of the outer ferroelectric material and extending along the channel top;

the outer conductive material and the outer ferroelectric material being discontinuous between immediately adjacent transistors along one of a) the collective row lines, and b) the collective column lines; and

the outer conductive material and the ferroelectric material being continuous between immediately adjacent transistors along the other of the collective row lines and the collective column lines.

23-36. -36. (canceled)