SEMICONDUCTOR DEVICE

• US 20160156347A1
• Filed: 03/10/2015
• Published: 06/02/2016
• Est. Priority Date: 11/28/2014
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: USUDA, Masayuki
• Application Number:
  US14/643,321
• Publication Number:
  US 20160156347A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 3/02 Regulating voltage or current
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

According to one embodiment, a semiconductor device includes a reference circuit configured to generate a bias voltage, a regulator configured to generate a regulator output based on the bias voltage and a power supply voltage, an integrated circuit to which the regulator output is supplied as a power supply, and a reset circuit configured to detect whether a difference between the bias voltage and the power supply voltage is equal to or higher than a threshold voltage and output a reset signal based on a detection result.

Claims

1. A semiconductor device comprising:

a reference circuit configured to generate a bias voltage;

a regulator configured to generate a regulator output based on the bias voltage and a power supply voltage;

an integrated circuit to which the regulator output is supplied as a power supply; and

a reset circuit configured to detect whether a difference between the bias voltage and the power supply voltage is equal to or higher than a threshold voltage and output a reset signal based on a detection result.

2. The semiconductor device according to claim 1, wherein

the reset circuit releases the reset of the integrated circuit by pulling up the reset signal to the power supply voltage based on the detection result.

3. The semiconductor device according to claim 1, wherein

the reset circuit includes a comparator configured to detect whether a difference between the bias voltage and the power supply voltage is equal to or higher than a threshold voltage, and

the comparator includes:

a current source configured to pull down the reset signal to a ground potential; and

a transistor to which a current is supplied from the current source and which is configured to pull up the reset signal to the power supply voltage.

4. The semiconductor device according to claim 1, wherein

the reset circuit includes a comparator configured to detect whether a difference between the bias voltage and the power supply voltage is equal to or higher than a threshold voltage,

the comparator includes:

a current source connected close to a ground potential side; and

a transistor connected in series to the current source and connected close to the power supply voltage side, and

the reset signal is output from a connection point between the current source and the transistor.

5. The semiconductor device according to claim 4, wherein

the threshold voltage of the comparator is a threshold voltage of the transistor.

6. The semiconductor device according to claim 4, wherein

the comparator includes:

a P-channel transistor of which the source is connected to the power supply voltage;

a first N-channel transistor connected in series to the P-channel transistor; and

a second N-channel transistor of which the gate is connected to a gate of the first N-channel transistor and the drain is connected to the gate, and to which a bias current is supplied via the drain.

7. The semiconductor device according to claim 4, wherein

the comparator includes:

a P-channel transistor of which the source is connected to the power supply voltage;

a first N-channel transistor connected in series to the P-channel transistor; and

a second N-channel transistor of which the gate is connected to a gate of the first N-channel transistor and the drain is connected to the gate, and to which a bias current is supplied from the power supply voltage to the drain via a resistor.

8. A semiconductor device comprising:

a reference circuit configured to generate a bias voltage;

a regulator configured to generate a regulator output based on the bias voltage and a power supply voltage;

an integrated circuit to which the regulator output is supplied as a power supply; and

a reset circuit configured to detect whether a difference between the regulator output and the power supply voltage is equal to or higher than a threshold voltage and output a reset signal based on a detection result.

9. The semiconductor device according to claim 8, wherein

the reset circuit releases the reset of the integrated circuit by pulling up the reset signal to the power supply voltage based on the detection result.

10. The semiconductor device according to claim 8, wherein

the reset circuit includes a comparator configured to detect whether a difference between the regulator output and the power supply voltage is equal to or higher than a threshold voltage, and

the comparator includes:

a current source configured to pull down the reset signal to a ground potential; and

a transistor to which a current is supplied from the current source and which is configured to pull up the reset signal to the power supply voltage.

11. The semiconductor device according to claim 8, wherein

the reset circuit includes a comparator configured to detect whether a difference between the regulator output and the power supply voltage is equal to or higher than a threshold voltage,

the comparator includes:

a current source connected close to a ground potential side; and

a transistor connected in series to the current source and connected close to the power supply voltage side, and

the reset signal is output from a connection point between the current source and the transistor.

12. The semiconductor device according to claim 11, wherein

a threshold voltage of the comparator is a threshold voltage of the transistor.

13. The semiconductor device according to claim 11, wherein

the comparator includes:

a P-channel transistor of which the source is connected to the power supply voltage;

a first N-channel transistor connected in series to the P-channel transistor; and

a second N-channel transistor of which the gate is connected to a gate of the first N-channel transistor and the drain is connected to the gate and to which a bias current is supplied via the drain.

14. The semiconductor device according to claim 11, wherein

the comparator includes:

a P-channel transistor of which the source is connected to the power supply voltage;

a first N-channel transistor connected in series to the P-channel transistor; and

a second N-channel transistor of which the gate is connected to a gate of the first N-channel transistor and the drain is connected to the gate, and to which a bias current is supplied from the power supply voltage to the drain via a resistor.

15. The semiconductor device according to claim 8, wherein

the regulator output is proportional to the bias voltage.

16. A semiconductor device comprising:

a reference circuit configured to generate a first bias voltage;

a regulator configured to generate a regulator output based on the first bias voltage and a power supply voltage;

an integrated circuit to which the regulator output is supplied as a power supply; and

a reset circuit configured to release the reset of the integrated circuit by pulling down a reset signal to a ground potential based on a second bias voltage generated separately from the first bias voltage.

17. The semiconductor device according to claim 16, wherein

the reset circuit includes:

a first current source configured to pull up the reset signal;

an N-channel transistor configured to pull down the reset signal; and

a second current source configured to operate at a lower voltage than the first current source and pull up the reset signal.

18. The semiconductor device according to claim 17, wherein

the first current source includes:

a first P-channel transistor which is connected in series to the N-channel transistor and of which the source is connected to the power supply voltage; and

a second P-channel transistor of which the gate is connected to a gate of the first P-channel transistor, the source is connected to the power supply voltage, and the drain is connected to the gate and to which a bias current is supplied via the drain, and

the second current source includes;

a third P-channel transistor which is connected in series to the N-channel transistor and of which the source is connected to the power supply voltage; and

a fourth P-channel transistor of which the gate is connected to a gate of the third P-channel transistor, the source is connected to the power supply voltage, and the drain is connected to the gate and to which a bias current is supplied to the drain via a resistor that is connected to the ground potential.

19. The semiconductor device according to claim 17, further comprising:

a switch circuit that turns off the second current source based on the reset signal.

20. The semiconductor device according to claim 19, wherein

the first current source includes:

a first P-channel transistor which is connected in series to the N-channel transistor and of which the source is connected to the power supply voltage; and

a second P-channel transistor of which the gate is connected to a gate of the first P-channel transistor, the source is connected to the power supply voltage, and the drain is connected to the gate and to which a bias current is supplied via the drain,

the second current source includes;

a third P-channel transistor connected in series to the N-channel transistor; and

a fourth P-channel transistor of which the gate is connected to a gate of the third P-channel transistor and the drain is connected to the gate and to which a bias current is supplied to the drain via a resistor that is connected to the ground potential,

the switch circuit includes;

a fifth P-channel transistor which is connected in series to the third P-channel transistor and of which the source is connected to the power supply voltage; and

a sixth P-channel transistor which is connected in series to the fourth P-channel transistor and of which the gate is connected to a gate of the fifth P-channel transistor and the source is connected to the power supply voltage, and

the reset signal is applied to the gates of the fifth and sixth P-channel transistors.