VECTOR PROCESSING ARCHITECTURES FOR INFRARED CAMERA ELECTRONICS

• US 20160156855A1
• Filed: 02/05/2016
• Published: 06/02/2016
• Est. Priority Date: 08/06/2013
• Status: Active Grant

• Current Assignee: Teledyne FLIR LLC (Teledyne Technologies Incorporated)
• Original Assignee: FLIR Systems, Inc. (Teledyne Technologies Incorporated)
• Inventors: Boulanger, Pierre, Roberts, Randy
• Granted Patent: US 10,070,074 B2
• Time in Patent Office: Days
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: H04N 23/20 for generating image signals from infrared radiation only
• CPC Class Codes: H04N 5/33 Transforming infrared radiation cameras or camera modules for generating image signals from infrared radiation H04N23/20; circuitry of SSIS for transforming infrared radiation into image signals H04N25/20
• CPC Class Codes: H04N 5/76 Television signal recording

Abstract

Systems and methods are disclosed herein to provide infrared imaging systems with improved electronics architectures. In one embodiment, an infrared imaging system is provided that includes an infrared imaging sensor for capturing infrared image data and a main electronics block for efficiently processing the captured infrared image data. The main electronics block may include a plurality of vector processors each configured to operate on multiple pixels of the infrared image data in parallel to efficiently exploit pixel-level parallelism. Each vector processor may be communicatively coupled to a local memory that provides high bandwidth, low latency access to a portion of the infrared image data for the vector processor to operate on. The main electronics block may also include a general-purpose processor configured to manage data flow to/from the local memories and other system functionalities. The main electronics block may be implemented as a system-on-a-chip.

Claims

1. An infrared imaging system comprising:

an infrared imaging sensor configured to provide infrared image data comprising a plurality of pixels; and

a main electronics block configured to receive the infrared image data, the main electronics block comprising at least one vector processor configured to operate on multiple pixels in parallel according to vector instructions associated with the at least one vector processor, wherein the multiple pixels are selected from the plurality of pixels of the infrared image data.

2. The infrared imaging system of claim 1, wherein:

the main electronics block further comprises;

at least one local memory communicatively coupled to the at least one vector processor and configured to store at least a portion of the infrared image data, and

a general-purpose processor configured to manage data flow to the at least one local memory; and

the at least one vector processors is configured to access the multiple pixels from the at least one local memory.

3. The infrared imaging system of claim 2, wherein the main electronics block is implemented as a system-on-a-chip (SOC) and further comprises a peripheral interface block configured to facilitate communications between the general-purpose processor and one or more peripheral devices.

4. The infrared imaging system of claim 2, further comprising a global memory communicatively coupled to the main electronics block and configured to store the infrared image data, wherein:

the main electronics block further comprises a direct memory access (DMA) engine responsive to DMA transfer requests from the general-purpose processor; and

the general-purpose processor is configured to manage data flow to the at least one local memory by requesting the DMA engine to perform a DMA transfer of the at least a portion of the infrared image data from the global memory to the at least one local memory.

5. The infrared imaging system of claim 1, wherein:

the at least one vector processor comprises a plurality of vector processors;

a first vector processor of the plurality of vector processors is configured to operate on a first multiple pixels in parallel according to first vector instructions associated with the first vector processor;

a second vector processor of the plurality of vector processors is configured to operate on a second multiple pixels in parallel according to second vector instructions associated with the second vector processor; and

the first and second multiple pixels are selected from the plurality of pixels of the infrared image data.

6. The infrared imaging system of claim 5, wherein the second multiple pixels comprise pixels that have been operated on by the first vector processor.

7. The infrared imaging system of claim 5, wherein the first vector instructions associated with the first vector processor are different from the second vector instructions associated with the second vector processor.

8. The infrared imaging system of claim 5, wherein:

the main electronics block further comprises a plurality of local memories;

a first local memory of the plurality of local memories is communicatively coupled to the first vector processor;

a second local memory of the plurality of local memories is communicatively coupled to the second vector processor;

the first vector processor is configured to access the first multiple pixels from the first local memory; and

the second vector processor is configured to access the second multiple pixels from the second local memory.

9. The infrared imaging system of claim 1, wherein:

the at least one vector processor comprises a plurality of vector processors; and

the vector instructions associated with the plurality of vector processors include instructions for performing offset correction, gain correction, bad pixel replacement, automatic gain control, and/or optical distortion correction on the multiple pixels in parallel.

10. The infrared imaging system of claim 9, wherein the vector instructions associated with the plurality of vector processors further include:

instructions for performing image/video resolution enhancement, image/video compression, and/or pixel-level operations of video analytics on the multiple pixels in parallel.

11. The infrared imaging system of claim 9, further comprising a visible light imaging sensor configured to provide visible light image data, wherein the vector instructions associated with the plurality of vector processors further include instructions for performing, on the multiple pixels in parallel, blending of the infrared image data with the visible light image data.

12. A method of providing infrared images, the method comprising:

converting received infrared energy into infrared image data comprising a plurality of pixels;

providing, to at least one vector processor, multiple pixels selected from the plurality of pixels of the infrared image data; and

operating on the multiple pixels in parallel at the at least one vector processor according to vector instructions associated with the at least one vector processor.

13. The method of claim 12, wherein:

the providing the multiple pixels comprises transferring at least a portion of the infrared image data to at least one local memory communicatively coupled to the at least one vector processor; and

the at least a portion of the infrared image data comprises the multiple pixels.

14. The method of claim 12, wherein:

the at least one vector processor comprises a plurality of vector processors;

the providing the multiple pixels comprises;

providing first multiple pixels selected from the plurality of pixels of the infrared image data to a first vector processor of the plurality of vector processors, and

providing second multiple pixels selected from the plurality of pixels of the infrared image data to a second vector processor of the plurality of vector processors; and

the operating on the multiple pixels comprises;

operating on the first multiple pixels in parallel at the first vector processor according to first vector instructions associated with the first vector processor, and

operating on the second multiple pixels in parallel at the second vector processor according to second vector instructions associated with the second vector processor.

15. The method of claim 14, wherein the second multiple pixels comprise pixels that have been operated on by the first vector processor.

16. The method of claim 14, wherein the first vector instructions associated with the first vector processor are different from the second vector instructions associated with the second vector processor.

17. The method of claim 14, wherein:

the providing the first multiple pixels comprises transferring the first multiple pixels to a first local memory communicatively coupled to the first vector processor; and

the providing the second multiple pixels comprises transferring the second multiple pixels to a second local memory communicatively coupled to the second vector processor.

18. The method of claim 12, wherein:

the at least one vector processor comprises a plurality of vector processors; and

the operating on the multiple pixels comprises performing offset correction, gain correction, bad pixel replacement, automatic gain control, and/or optical distortion correction on the multiple pixels in parallel.

19. The method of claim 18, wherein the operating on the multiple pixels further comprises performing image/video resolution enhancement, image/video compression, and/or pixel-level operations of video analytics on the multiple pixels in parallel.

20. The method of claim 18, further comprising converting received visible light into visible light image data, wherein the operating on the multiple pixels further comprises performing, on the multiple pixels in parallel, blending of the infrared image data with the visible light image data.