PARALLEL OPERATION SYSTEM, APPARATUS AND MEDIUM

• US 20160161981A1
• Filed: 12/02/2015
• Published: 06/09/2016
• Est. Priority Date: 12/05/2014
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: SAKURAI, Ryota
• Granted Patent: US 9,891,655 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 15/17325 Synchronisation; Hardware support therefor intertask synchronisation G06F9/52
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A parallel operation system includes a first node including a first processor configured to execute a first process, a second processor configured to execute a second process, and a first memory, and a second node including a third processor configured to execute a third process, a fourth processor configured to execute a fourth process, and a second memory, and a first signal line that transfers synchronization information between at least one of the first and second processors and at least one of the third and fourth processors, wherein when the first process is to be synchronized with the third process, at least one of the first and the third processors using the first signal line to execute a first synchronization process.

Claims

1. A parallel operation system comprising:

a first node including

a first processor configured to execute a first process,

a second processor configured to execute a second process, and

a first memory, and

a second node including

a third processor configured to execute a third process,

a fourth processor configured to execute a fourth process, and

a second memory, and

a first signal line that transfers synchronization information between at least one of the first and second processors and at least one of the third and fourth processors, wherein when the first process is to be synchronized with the third process, at least one of the first and the third processors using the first signal line to execute a first synchronization process.

2. The system according to claim 1, wherein

the first synchronization process is a CPU synchronization process which performs synchronization between the first process and the third process using the first signal line.

3. The system according to claim 1, wherein

when the first process and the second process is to be synchronized in the first node, at least one of the first and the second processors execute a second synchronization process using the first memory.

4. The system according to claim 3, wherein

the first node includes a second signal line that transfers synchronization information between the first processor and the second processor, and

the at least one of the first and second processors is configured to:

when the first process and the second process is to be synchronized in the first node, compare a processing performance of a third synchronization process that synchronizes the first process and the second process by using the second signal line, with a processing performance of the second synchronization process,

determine one of the third synchronization process and the second synchronization process is to be executed by the at least one of the first and second processors, based on the comparison, and

execute the determined one of the third synchronization process and the second synchronization process.

5. The system according to claim 4, wherein

the performance of the second synchronization process is based on an access speed for the at least one of the first and second processors to access the first memory.

6. The system according to claim 4, wherein

the performance of the second synchronization process is based on a size of the first memory used for the second synchronization process.

7. The system according to claim 4, wherein

the first process repeats a first predetermined process,

the second process repeats a second predetermined process, and

the at least one of the first and second processors is configured to:

determine one of the third synchronization process and the second synchronization process, based on the comparison and the number of times the first process repeats the first predetermined process and the second process repeats the second predetermined process.

8. An apparatus comprising:

a memory; and

a processor coupled to the memory and configured to;

determine, when a first processor that executes a first process and a second processor that executes a second process belong to different nodes in a parallel operation system, to execute a first synchronization process to synchronize the first process and the second process using a signal line which couples the first processor and the second processor, the parallel operation system including a plurality of nodes including the different nodes; and

cause at least one of the first processor and the second processor to execute the first synchronization process based on the determination of executing the first synchronization process.

9. The apparatus according to claim 8, wherein the processor is configured to:

determine, when the first processor and the second processor is included in a same node among the plurality of nodes, to execute a second synchronization process using a memory included in the same node; and

cause the at least one of the first processor and the second processor to execute the second synchronization based on the determination of executing the second synchronization process.

10. The apparatus according to claim 9, wherein

the processor is configured to:

when the first processor and the second processor belong to the same node, compare a processing performance of a third synchronization process using the signal line that couples the first and the second processors in the same node with a processing performance of the second synchronization process,

determine one of the third synchronization process and the second synchronization process is to be executed by at least one of the first processor and the second processor, based on the comparison, and

cause the at least one of the first processor and the second processor to execute the determined one of the third synchronization process and the second synchronization process.

11. The apparatus according to claim 10, wherein

the performance of the second synchronization process is based on an access speed for the at least one of the first processor and the second processor to access the memory.

12. The apparatus according to claim 10, wherein

the performance of the second synchronization process is based on a size of the memory used for the second synchronization process.

13. The apparatus according to claim 10, wherein

the first process repeats a first predetermined process,

the second process repeats a second predetermined process, and

the processor is configured to:

determine one of the third synchronization process and the second synchronization process, based on the comparison result and the number of times the first process repeats the first predetermined process and the second process repeats the second predetermined process.

14. The apparatus according to claim 8, wherein

the processor is one of the first processor and the second processor.

15. A non-transitory computer readable medium having stored therein a program that causes a computer to execute:

determining, when a first processor that executes a first process and a second processor that executes a second process belong to different nodes in a parallel operation system, to execute a first synchronization process to synchronize the first process and the second process using a signal line which couples the first processor and the second processor, the parallel operation system including a plurality of nodes including the different nodes; and

causing at least one of the first processor and the second processor to execute the first synchronization process based on the determination of executing the first synchronization process.

16. The non-transitory computer readable medium according to claim 15, wherein the computer further executes:

determining, when the first processor and the second processor is included in a same node among the plurality of nodes, to execute a second synchronization process using a memory included in the same node; and

causing the at least one of the first processor and the second processor to execute the second synchronization based on the determination of executing the second synchronization process.

17. The non-transitory computer readable medium according to claim 16, wherein the computer further executes:

when the first processor and the second processor belong to the same node, comparing a processing performance of a third synchronization process using the signal line that couples the first and the second processors in the same node with a processing performance of the second synchronization process,

determining one of the third synchronization process and the second synchronization process is to be executed by at least one of the first processor and the second processor, based on the comparison, and

causing the at least one of the first processor and the second processor to execute the determined one of the third synchronization process and the second synchronization process.

18. The non-transitory computer readable medium according to claim 17, wherein the performance of the second synchronization process is based on an access speed for the at least one of the first processor and the second processor to access the memory.

19. The non-transitory computer readable medium according to claim 17, wherein the performance of the second synchronization process is based on a size of the memory used for the second synchronization process.

20. The non-transitory computer readable medium according to claim 17, wherein

the first process repeats a first predetermined process,

the second process repeats a second predetermined process, and

the computer further executes:

determining one of the third synchronization process and the second synchronization process, based on the comparison result and the number of times the first process repeats the first predetermined process and the second process repeats the second predetermined process.