SYSTEMS AND METHODS FOR MULTI-ZONE DATA TIERING FOR ENDURANCE EXTENSION IN SOLID STATE DRIVES

• US 20160162354A1
• Filed: 12/04/2014
• Published: 06/09/2016
• Est. Priority Date: 12/04/2014
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: HGST Netherlands B.V. (Western Digital Corporation)
• Inventors: SINGHAI, Ashish, KARAMCHETI, Vijay, NARASIMHA, Ashwin
• Granted Patent: US 10,691,531 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/353 Adaptation to the channel
• CPC Class Codes: H03M 13/356 Unequal error protection [UEP]

Abstract

Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.

Claims

1. A method for increasing the endurance of a solid state drive having a plurality of blocks by assigning different levels of error protection, the method comprising:

providing a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels;

associating a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone;

assigning a first error correction mechanism and a first corresponding error correction level to the first zone; and

assigning a second error correction mechanism and a second corresponding error correction level to the second zone.

2. The method of claim 1, further comprising re-associating a first block from the first plurality of blocks with the second zone, if the first block has an error count number higher than a threshold error count number.

3. The method of claim 1, further comprising re-associating a second block from the second plurality of blocks with the first zone, if the second block has an error count number lower than a threshold error count number.

4. The method of claim 1, further comprising re-assigning to the first zone the first error correction mechanism and a third corresponding error correction level, wherein the first error correction mechanism and the third corresponding error correction level provide higher error correction from the first error correction mechanism and the first corresponding error correction level.

5. The method of claim 1, further comprising re-assigning to the first zone a third error correction mechanism and the first corresponding error correction level, wherein the third error correction mechanism and the first corresponding error correction level provide higher error correction from the first error correction mechanism and the first corresponding error correction level.

6. The method of claim 1, wherein the first zone has a higher endurance than the second zone.

7. The method of claim 6, further comprising directing a first plurality of write requests to the solid state drive into the first zone and a second plurality of write requests into the second zone;

wherein the write requests of the first plurality of write requests generate higher write amplification than the write requests of the second plurality of write requests.

8. The method of claim 7, further comprising re-directing at least one write request from the first plurality of write requests into the second zone.

9. The method of claim 1, wherein the first zone covers at least 10% of the solid state drive capacity.

10. The method of claim 1, further comprising filtering out write requests with random traffic patterns from the second zone.

11. The method of claim 1, wherein the solid state drive is a multi-level cell flash device.

12. The method of claim 11, further comprising dividing the multi-level cell flash device into at least one region, wherein the at least one region is in a single-level cell mode.

13. The method of claim 12, wherein the first zone is assigned to the at least one region.

25. The memory controller of claim 11, further comprising dividing the multi-level cell flash device into at least one region, wherein the at least one region is in a single-level cell mode.

26. The memory controller of claim 25, wherein the first zone is assigned to the at least one region.

14. A memory controller comprising:

a controller module configured to;

communicate with a solid state drive having a plurality of blocks;

provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels;

associate a first plurality of blocks of a solid state drive having a plurality of blocks and in communication with the memory controller with a first zone and a second plurality of blocks of the solid state drive with a second zone;

assign a first error correction mechanism and a first corresponding error correction level to the first zone; and

assign a second error correction mechanism and a second corresponding error correction level to the second zone.

15. The memory controller of claim 14, wherein the controller module is further configured to re-associate a first block from the first plurality of blocks with the second zone, if the first block has an error count number higher than a threshold error count number.

16. The memory controller of claim 14, wherein the controller module is further configured to re-associate a second block from the second plurality of blocks with the first zone, if the second block has an error count number lower than a threshold error count number.

17. The memory controller of claim 14, wherein the controller module is further configured to re-assign to the first zone the first error correction mechanism and a third corresponding error correction level, wherein the first error correction mechanism and the third corresponding error correction level provide higher error correction from the first error correction mechanism and the first corresponding error correction level.

18. The memory controller of claim 14, wherein the controller module is further configured to re-assign to the first zone a third error correction mechanism and the first corresponding error correction level, wherein the third error correction mechanism and the first corresponding error correction level provide higher error correction from the first error correction mechanism and the first corresponding error correction level.

19. The memory controller of claim 14, wherein the first zone has a higher endurance than the second zone.

20. The memory controller of claim 19, wherein the controller module is further configured to direct a first plurality of write requests to the solid state drive into the first zone and a second plurality of write requests into the second zone;

wherein the write requests of the first plurality of write requests generate higher write amplification than the write requests of the second plurality of write requests.

21. The memory controller of claim 20, wherein the controller module is further configured to re-direct at least one write request from the first plurality of write requests into the second zone.

22. The memory controller of claim 14, wherein the first zone covers at least 10% of the solid state drive capacity.

23. The memory controller of claim 14, wherein the controller module is further configured to filter out write requests with random traffic patterns from the second zone.

24. The memory controller of claim 14, wherein the solid state drive is a multi-level cell flash device.