METHODS, CIRCUITS, DEVICES, SYSTEMS AND MACHINE EXECUTABLE CODE FOR READING FROM A NON-VOLATILE MEMORY ARRAY

• US 20160162355A1
• Filed: 12/08/2014
• Published: 06/09/2016
• Est. Priority Date: 12/08/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Mizrachi, Kfir, Kalderon, Ifat Nitzan, Zitlaw, Clifford Alan
• Granted Patent: US 9,632,867 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Disclosed is a method for reading from a non-volatile memory (NVM) device including: retrieving a set of data from an NVM array according to a read sequence for a requested set of logical memory locations received from a host device, detecting errors in the set of data, preparing an error indicator to be output to a host device substantially upon detection of the errors and outputting the error indication in response to a command being received from the host device.

Claims

1. A non-volatile memory (NVM) array control circuit comprising:

a data reading circuit block adapted to read a set of physical memory locations on the NVM array which correspond to a set of logical memory locations requested by a host device; and

an error detection circuit block to signal the host device of one or more detected read errors substantially upon detection and prior to completing a read sequence for the requested set of logical memory locations.

2. The NVM array control circuit of claim 1, further comprising one or more error-type sub-circuits to indicate a type of read error detected.

3. The NVM array control circuit according to claim 2, wherein said sub-circuits are selected from the group consisting of:

a register, a counter, volatile memory and a state machine.

4. The NVM array control circuit of claim 2, wherein said type of read error is selected from the group consisting of:

a one bit error, a two bit error and a multiple bit error.

5. The NVM array control circuit of claim 1, further comprising one or more error-count sub-circuits to indicate a number of read errors in the requested set.

6. The NVM array of claim 5, wherein said sub-circuits are selected from the group consisting of:

a register, a counter, volatile memory and a state machine.

7. The NVM array control circuit of claim 5, wherein said number of read errors is selected from:

number of errors per sub-read section, number of errors of an error type;

number of errors within a predetermined period of time and number of errors within a predetermined section.

8. The NVM array control circuit of claim 1, further comprising one or more address sub-circuits to indicate one or more memory locations associated with a detected read error.

9. The NVM array control circuit of claim 8, wherein said one or more memory locations are at least partially dependent on the memory locations selected from the group consisting of:

a logical memory location of the first error detected, a logical memory location of the last error detected and a logical memory location of the first 2-bit error detected.

10. The NVM array control circuit of claim 1, further configured to output detected error information through one or more dedicated pins.

11. The NVM array control circuit of claim 10, wherein said detected error information is output responsive to a received command from the host device.

12. The NVM array control circuit of claim 1, further configured to output detected error information through one or more multi-purpose pins.

13. The NVM array control circuit of claim 12, wherein said detected error information is output responsive to a received command from the host device.

14. The NVM array control circuit of claim 1, wherein said data reading circuit block is further configured to stop reading a requested set of data based on an input received from the host device responsive to a detected error.

15. A method for reading from a non-volatile memory (NVM) device comprising:

retrieving a set of data from an NVM array according to a read sequence for a requested set of logical memory locations received from a host device;

detecting errors in said set of data;

preparing an error indicator to be output to a host device; and

outputting said error indication in response to a command being received from the host device.

16. The method according to claim 15, further comprising indicating a type of read error detected.

17. The method according to claim 15, further comprising indicating a number of read errors in the requested set.

18. The method according to claim 15, further comprising indicating one or more memory locations associated with a detected read error.

19. The method according to claim 15, wherein said outputting is selected from the group consisting of:

outputting responsive to a received command from the host device;

outputting dependent on exiting of a read sequence;

outputting dependent on aborting a read sequence.

20. The method according to claim 15, further comprising stopping a read sequence based on an input received from the host device responsive to a detected error.

21. A host device associated with a primary apparatus and a non-volatile memory (NVM) device, the host device comprising:

a data controller to;

(a) provide a set of logical memory locations to the NVM device and request to read information stored in said set;

(b) receive at least a segment of said read information; and

(c) if said NVM detects an error, receive a read error indication substantially upon detection by the NVM substantially prior to completing a read sequence for the requested set of logical memory locations; and

primary apparatus control circuitry to control at least one electro-mechanical functionality of the primary apparatus dependent on a received read error indication.

22. The host device according to claim 21, wherein said primary apparatus is a vehicle and said primary apparatus control circuitry is further, configured to disable a functionality of the primary apparatus if a 2-bit error indication is received from the NVM device.

23. The host device according to claim 21, wherein said data controller is further configured to respond to the read error indication with one or more control signals to trigger the NVM device to relay additional error information to said controller wherein said additional error information is one or more types of information selected from the group consisting of:

number of errors, logical memory location associated with an error detection and error detection type.