LITHOGRAPHY PROCESS WINDOW PREDICTION BASED ON DESIGN DATA

• US 20160162626A1
• Filed: 02/12/2016
• Published: 06/09/2016
• Est. Priority Date: 12/01/2014
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Herrmann, Thomas, Schueler, Stefan, Samy, Aravind Narayana
• Application Number:
  US15/042,779
• Publication Number:
  US 20160162626A1
• Time in Patent Office: Days
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 7/70441 Optical proximity correction [OPC]
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70641 Focus
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method of manufacturing a semiconductor device, comprising providing design data, producing lithography masks based on the design data, predicting a product process window and producing a wafer including semiconductor structures by means of the lithography masks and observing conditions defined by the product process window.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing design data;

producing lithography masks based on said design data;

predicting a product process window; and

producing a wafer including semiconductor structures by means of said lithography masks and observing conditions defined by said product process window.

2. The method of claim 1, wherein said predicting of said product process window comprises generating a plurality of process windows for a plurality of known layout configurations and generating said product process window based on said generated plurality of process windows.

3. The method of claim 1, wherein said predicting of said product process window comprises simulating a topography of a wafer based on said design data and determining a tolerable range of depth of focus based on said simulated topography.

4. The method of claim 1, wherein said predicting of said product process window comprises measuring mask CDs of said produced lithography masks and determining a tolerable range of exposure doses based on said measured mask CDs.

5. The method of claim 1, wherein said predicting of said product process window comprises simulating a topography of a wafer based on said design data and determining a tolerable range of depth of focus based on said simulated topography and wherein simulating said topography of said wafer comprises using a CMP model based on CMP process parameters thereby taking into account a CMP induced wafer topology.

6. The method of claim 1, further comprising:

designing photolithography masks based on said provided design data; and

wherein said predicting of said product process window comprises generating a plurality of process windows for a plurality of known layout configurations and based on design rule checks performed for said plurality of known layout configurations and said designed photolithography masks and generating said product process window based on said generated plurality of process windows.

7. The method of claim 1, further comprising inspecting said produced wafer for generating a process window based on said wafer inspection and adding said process window to a plurality of stored process windows for a plurality of known layout configurations.

8. The method of claim 1, wherein said predicting of said product process window comprises:

a) reading or generating a first plurality of process windows for a plurality of known layout configurations, each of said first plurality of process windows defining tolerable ranges of depth of focus and exposure doses;

b) simulating a topography of a wafer based on said design data and determining a tolerable range of depth of focus based on said simulated topography for each of said first plurality of process windows;

c) measuring mask CDs of said produced lithography masks and determining a tolerable range of exposure doses based on said measured mask CDs for each of said first plurality of process windows;

d) generating a second plurality of process windows based on said first plurality of process windows, said determined tolerable ranges of depth of focus and said determined tolerable ranges of exposure doses; and

e) combining said second plurality of process windows to generate said product process window.

9. The method of claim 8, wherein said generating of said second plurality of process windows comprises, for each of said second plurality of process windows, defining:

an upper boundary of tolerable values of depth in focus by the minimum of the respective maximum values of the tolerable values of depth in focus of the corresponding process window of said first plurality of process windows and the corresponding range of depth of focus determined based on said simulated topography;

an upper boundary of tolerable values of exposure doses by the minimum of the respective maximum values of the tolerable values of exposure doses of the corresponding process window of said first plurality of process windows and the corresponding range of exposure doses determined based on said measured mask CDs;

a lower boundary of tolerable values of depth in focus by the maximum of the respective minimum values of the tolerable values of depth in focus of the corresponding process window of said first plurality of process windows and the corresponding range of depth of focus determined based on said simulated topography; and

a lower boundary of tolerable values of exposure doses by the maximum of the respective minimum values of the tolerable values of exposure doses of the corresponding process window of said first plurality of process windows and the corresponding range of exposure doses determined based on said measured mask CDs.

10. A lithography method for manufacturing an integrated circuit, comprising:

providing a design data comprising layouts for semiconductor devices;

designing and producing photolithography masks based on said design data;

predicting a product process window; and

producing a wafer including said semiconductor devices forming said integrated circuit based on said produced photolithography masks and said predicted product process window.

11. The method of claim 10, wherein predicting said product process window comprises reading a plurality of known layout configurations and reading or generating a first plurality of process windows for said plurality of known layout configurations.

12. The method of claim 11, further comprising:

simulating a topography of a wafer based on said design data and determining a tolerable range of depth of focus based on said simulated topography; and

measuring mask CDs of the produced lithography masks and determining a tolerable range of exposure doses based on said measured mask CDs; and

wherein said product process window is predicted based on said determined tolerable ranges of depth of focus and exposure doses.

13. The method according to claim 11, further comprising:

simulating a topography of a wafer based on said design data and determining a tolerable range of depth of focus based on said simulated topography;

measuring mask CDs of said produced lithography masks and determining a tolerable range of exposure doses based on said measured mask CDs;

generating a second plurality of process windows based on said first plurality of process windows and said determined tolerable ranges of depth of focus and exposure doses; and

combining the process windows of said second plurality of process windows to generate said product process window.