METHOD OF DRIVING A DISPLAY PANEL AND A DISPLAY APPARATUS FOR PERFORMING THE SAME

• US 20160163287A1
• Filed: 08/26/2015
• Published: 06/09/2016
• Est. Priority Date: 12/04/2014
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: AHN, Ik-Hyun, Seo, Jung-Deok, Park, Bong-im
• Granted Patent: US 9,947,295 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2230/00 Details of flat display driving waveforms
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2310/067 Special waveforms for scanning, where no circuit details of the gate driver are given
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/0693 Calibration of display systems
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players

Abstract

A method of driving a display device including a display panel is provided. The display panel includes a plurality of gate lines. The gate lines are divided into a plurality of gate line groups. The method includes applying different gate delay values to each of the gate line groups to generate gate signals and outputting the gate signals to the gate lines. A first gate delay value is applied to at least one of the gate lines during a first frame and a second gate delay value different from the first delay value is applied to the at least one of the gate lines during a second frame.

Claims

1. A method of driving a display device including a display panel, wherein the display panel includes a plurality of gate lines, the method comprising:

applying different gate delay values to each of the plurality of gate line groups to generate gate signals, the gate lines of the display panel divided into the gate line groups; and

outputting the gate signals to the gate lines,

wherein a first gate delay value is applied to at least one of the gate lines during a first frame, and a second gate delay value different from the first gate delay value is applied to the at least one of the gate lines during a second frame.

2. The method of claim 1, wherein a gate delay value applied to a P-th gate line group of the gate line groups is less than a gate delay value applied to a Q-th gate line group of the gate line groups, the P-th gate line group being closer than the Q-th gate line group to a data driver of the display device, and

wherein P and Q are positive integers.

3. The method of claim 2, wherein a gate delay value applied to the P-th gate line group during the first frame is X, a gate delay value applied to the P-th gate line group during the second frame is (X+a), and

wherein X and a are positive real numbers.

4. The method of claim 3, wherein a gate delay value applied to the P-th gate line group during a third frame is (X−

a).

5. The method of claim 2, wherein a gate delay value applied to the P-th gate line group during the first frame is X, a gate delay value applied to a first gate line of the P-th gate line group during the second frame is (X+a), and a gate delay value applied to gate lines of the P-th gate line group except for the first gate line of the P-th gate line group during the second frame is X, and

wherein X and a are positive real numbers.

6. The method of claim 2, wherein a last gate line in the P-th gate line group is a Y-th gate line of the gate lines during the first frame, and

the last gate line of the P-th gate line group is a (Y+b)-th gate line of the gate lines during the second frame, and

wherein Y and b are positive integers.

7. The method of claim 6, wherein the last gate line of the P-th gate line group is a (Y−

b)-th gate line of the gate lines during a third frame.

8. The method of claim 1, wherein a gate clock signal is generated based on the first gate delay value or the second gate delay value, and

the gate signals are generated based on the gate clock signal.

9. The method of claim 1, wherein the gate signals are synchronized with a load signal corresponding to an output timing of a data voltage to a data line of the display device, and

the first gate delay value or the second gate delay value is defined with respect to the load signal.

10. A display apparatus comprising:

a display panel including a plurality of gate lines and a plurality of data lines, the gate lines divided into a plurality of gate line groups;

a gate driver configured to apply different gate delay values to each of the gate line groups to generate gate signals and to output the gate signals to the gate lines;

a data driver configured to output data voltages to the data lines; and

a signal controller configured to control the gate driver and the data driver,

wherein a first gate delay value is applied to at least one of the gate lines during a first frame, and a second gate delay value different from the first gate delay value is applied to the at least one of the gate lines during a second frame.

11. The display apparatus of claim 10, wherein a gate delay value applied to a P-th gate line group of the gate line groups is less than a gate delay value applied to a Q-th gate line group of the gate line groups, the P-th gate line group being closer than the Q-th gate line group to a data driver of the display device, and

wherein P and Q are positive integers.

12. The display apparatus of claim 11, wherein a gate delay value applied to the P-th gate line group during the first frame is X, a gate delay value applied to the P-th gate line group during the second frame is (X+a), and

wherein X and a are positive real numbers.

13. The display apparatus of claim 12, wherein a gate delay value applied to the P-th gate line group during a third frame is (X−

a).

14. The display apparatus of claim 11, wherein a gate delay value applied to the P-th gate line group during the first frame is X,

a gate delay value applied to a first gate line of the P-th gate line group during the second frame is (X+a), and a gate delay value applied to gate lines of the P-th gate line group except for the first gate line of the P-th gate line group during the second frame is X, and

wherein X and a are positive real numbers.

15. The display apparatus of claim 11, wherein a last gate line of the P-th gate line group is a Y-th gate line of the gate lines during the first frame, and the last gate line of the P-th gate line group is a (Y+b)-th gate line of the gate lines during the second frame, and

wherein Y and b are positive integers.

16. The display apparatus of claim 15, wherein the last gate line of the P-th gate line group is a (Y−

b)-th gate line of the gate lines during a third frame.

17. The display apparatus of claim 10, wherein the signal controller is configured to generate a gate clock signal based on the first gate delay value or the second gate delay value, and

the gate driver is configured to generate the gate signals based on the gate clock signal.

18. The display apparatus of claim 10, wherein the signal controller is configured to generate a load signal corresponding to output timings of the data voltages to the data lines,

the gate signals are synchronized with the load signal, and

the first gate delay value or the second gate delay value is defined with respect to the load signal.

19. A method of driving a display device including a display panel, wherein the display panel includes a plurality of gate lines including a plurality of gate line groups, the method comprising:

applying different gate delay values to each of the plurality of gate line groups to generate gate signals; and

outputting the gate signals to the gate lines,

wherein a gate delay value applied to a P-th gate line group of the gate line groups is less than a gate delay value of a Q-th gate line group of the gate line groups, the P-th gate line group being closer than the Q-th gate line group to a data driver of the display device, and

wherein P and Q are positive integers.

20. The method of claim 19, wherein a first gate delay value is applied to at least one of the gate lines during a first frame, and a second gate delay value different from the first gate delay value is applied to the at least one of the gate lines during a second frame.

21. The method of claim 20, wherein a gate clock signal is generated based on the first gate delay value or the second gate delay value, and

the gate signals are generated based on the gate clock signal.

22. The method of claim 19, wherein a gate delay value applied to the P-th gate line group during a first frame is X, a gate delay value applied to the P-th gate line group during a second frame is (X+a), and a gate delay value applied to the P-th gate line group during a third frame is (X−

a), and

wherein X and a are positive real numbers.

23. The method of claim 19, wherein the gate signals are synchronized with a load signal corresponding to an output timing of a data voltage to a data line of the display device.