APPARATUSES INCLUDING MEMORY ARRAYS WITH SOURCE CONTACTS ADJACENT EDGES OF SOURCES

• US 20160163726A1
• Filed: 02/11/2016
• Published: 06/09/2016
• Est. Priority Date: 03/07/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Granted Patent: US 10,050,049 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor

Abstract

Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. Each of the at least two memory arrays can include memory cells, control gates, and data lines. There is no data line between an edge of a source and the source contacts adjacent the edge.

Claims

1. An apparatus, comprising:

source plates respectively coupled to memory arrays; and

a source conductor coupled to the source plates through source contacts adjacent to edges of the source plates, wherein a source contact of the source contacts includes a first contact electrically coupled to the source conductor, a second contact electrically coupled to a source plate of the source plates, and a conductive connector connecting the first contact and the second contact.

2. The apparatus of claim 1, wherein a memory array of the memory arrays includes vertical strings of memory cells, control gates, and data lines.

3. The apparatus of claim 1, wherein there is no data line between a source contact of the source contacts and an edge of the edges of the source plates adjacent to the source contact.

4. The apparatus of claim 1, wherein the source plates comprise metal material.

5. The apparatus of claim 1, wherein the source plates comprise WSi material.

6. The apparatus of claim 1, wherein the source plates comprise a stack of metal material and polysilicon.

7. The apparatus of claim 1, wherein the source plates comprise a stack of WSi material and polysilicon.

8. An apparatus comprising:

a source plate supporting and electrically coupled to a memory array;

a source conductor extending over the memory array and coupled to the source plate through a source contact adjacent to an edge of the source plate; and

an interconnection component extending perpendicular to the source conductor and coupled to the source conductor through an interconnection contact.

9. The apparatus of claim 8, wherein the memory array includes vertical strings of memory cells, control gates, and data lines.

10. The apparatus of claim 9, wherein there is no data line between the source contact and the edge of the source plate adjacent to the source contact.

11. The apparatus of claim 9, wherein the source contact is adjacent to the edge of the source along a control gate direction.

12. The apparatus of claim 8, wherein the interconnection component extends below the source plate.

13. The apparatus of claim 8, wherein the interconnection component extends over the source conductor.

14. The apparatus of claim 8, wherein the interconnection contact includes a first contact electrically coupled to the source conductor, a second contact electrically coupled to the interconnection component, and a third contact connecting the first contact and the second contact.

15. The apparatus of claim 8, wherein the interconnection contact comprises a single conductive plug.

16. An apparatus comprising:

source plates respectively coupled to memory arrays;

a source conductor formed over the memory arrays, and coupled to the source plates through source contacts adjacent edges of the source plates; and

a signal conductor parallel with the source conductor, and coupled to control gates of the memory arrays to provide control signals to the memory arrays.

17. The apparatus of claim 16, wherein the memory arrays are formed on a same semiconductor substrate.

18. The apparatus of claim 17, wherein the semiconductor substrate comprises silicon.

19. The apparatus of claim 16, wherein there is no source routing inside any of the memory arrays.

20. The apparatus of claim 16, wherein a source contact of the source contacts includes a first contact electrically coupled to the source conductor, a second contact electrically coupled to a source plate of the source plates, and a conductive connector connecting the first contact and the second contact.