IMAGE SENSOR CHIP SIDEWALL INTERCONNECTION

• US 20160163755A1
• Filed: 12/09/2014
• Published: 06/09/2016
• Est. Priority Date: 12/09/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Kuo-Chin, Chen, Pao-Tung, Chiang, Wei-Chieh, Hashimoto, Kazuaki, Liu, Jen-Cheng
• Granted Patent: US 9,634,053 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration

Abstract

An image sensor chip having a sidewall interconnect structure to bond and/or electrically couple the image sensor chip to a package substrate is provided. The image sensor chip includes a substrate supporting an integrated circuit (IC) configured to sense incident light. The sidewall interconnect structure is arranged along a sidewall of the substrate and electrically coupled with the IC. A method for manufacturing the image sensor chip and an image sensor package including the image sensor chip are also provided.

Claims

1. An image sensor chip comprising:

a substrate supporting an integrated circuit (IC) configured to sense incident light; and

a sidewall interconnect structure arranged along a sidewall of the substrate and electrically coupled with the IC.

2. The image sensor chip according to claim 1, further including:

a through silicon via (TSV) extending through the substrate to the IC and configured to electrically couple the sidewall interconnect structure to the IC.

3. The image sensor chip according to claim 2, further including:

a conductive layer arranged below the substrate and configured to electrically connect the TSV and the sidewall interconnect structure.

7. The image sensor chip according to claim 1, further including:

a back-end-of-line (BEOL) metallization stack arranged over the substrate; and

a device layer arranged over the substrate and electrically coupled to the sidewall interconnect structure through the BEOL metallization stack.

8. The image sensor chip according to claim 7, further including:

a second substrate arranged over the BEOL metallization stack, wherein the device layer is arranged between the second substrate and the BEOL metallization stack.

21. The image sensor chip according to claim 2, further comprising:

a back-end-of-line (BEOL) metallization stack arranged over the substrate and comprising an image sensor bond pad, wherein the image sensor bond pad is arranged within an interlayer dielectric (ILD) layer of the BEOL metallization stack; and

an opening extending through the substrate, into the ILD layer, to expose the image sensor bond pad, wherein the TSV is arranged in the opening.

22. The image sensor chip according to claim 21, wherein the TSV comprises:

a dielectric layer lining sidewalls of the opening; and

a conductive layer lining the opening and contacting the image sensor bond pad, wherein the conductive layer is insulated from the substrate by the dielectric layer.

23. The image sensor chip according to claim 21, wherein a portion of the opening is unfilled.

24. The image sensor chip according to claim 21, further comprising:

a recess extending laterally into a sidewall of the substrate; and

a conductive layer continuously lining the opening and the recess, wherein the conductive layer contacts the image sensor bond pad.

25. The image sensor chip according to claim 8, further comprising:

a transparent plate arranged over and bonded to the second substrate through an epoxy layer.

4-6. -6. (canceled)

9-19. -19. (canceled)

20. An image sensor package comprising:

a package substrate having a package bond pad;

an image sensor chip arranged over the package substrate, the image sensor chip including an integrated circuit (IC) electrically coupled with a sidewall interconnect structure arranged along a sidewall of the image sensor chip; and

an electrical coupling structure arranged over the package bond pad along the sidewall of the image sensor chip and configured to electrically couple the IC to the package bond pad through the sidewall interconnect structure.

26. The image sensor package according to claim 20, wherein a lower surface of the image sensor chip directly contacts an upper surface of the package bond pad.

27. The image sensor package according to claim 20, further comprising:

a housing structure supporting an optical lens over the image sensor chip, wherein the optical lens is configured to focus incident light on the image sensor chip.

28. The image sensor package according to claim 20, wherein the image sensor chip comprises:

a substrate supporting the IC, wherein the IC is configured to sense incident light; and

a through silicon via (TSV) extending through the substrate to the IC and configured to electrically couple the sidewall interconnect structure to the IC.

29. The image sensor package according to claim 28, wherein the image sensor chip further comprises:

a conductive layer arranged below the substrate and configured to electrically couple the TSV and the sidewall interconnect structure.

30. The image sensor package according to claim 28, wherein the image sensor chip comprises:

a back-end-of-line (BEOL) metallization stack arranged over the substrate and comprising an image sensor bond pad, wherein the image sensor bond pad is arranged within an interlayer dielectric (ILD) layer of the BEOL metallization stack; and

an opening extending through the substrate, into the ILD layer, to expose the image sensor bond pad, wherein the TSV is arranged in the opening.

31. The image sensor package according to claim 30, wherein the image sensor chip comprises:

a recess extending laterally into a sidewall of the substrate; and

a conductive layer lining the opening and the recess, wherein the conductive layer contacts the image sensor bond pad, and wherein the conductive layer extends continuously from the opening to the recess.

32. The image sensor package according to claim 20, wherein the image sensor chip comprises:

a substrate supporting the IC, wherein the IC is configured to sense incident light;

a back-end-of-line (BEOL) metallization stack arranged over the substrate; and

a second substrate arranged over the BEOL metallization stack; and

a device layer arranged over the BEOL metallization stack, between the second substrate and the BEOL metallization stack, wherein the device layer is electrically coupled to the sidewall interconnect structure through the BEOL metallization stack.

33. The image sensor package according to claim 20, further comprising:

a transparent plate arranged over and bonded to the image sensor chip through an epoxy layer.

34. An image sensor chip, comprising:

a back-end-of-line (BEOL) metallization stack arranged over a first substrate, wherein an image sensor bond pad is arranged within an interlayer dielectric (ILD) layer of the BEOL metallization stack;

a second substrate arranged over the BEOL metallization stack;

a device layer arranged over the BEOL metallization stack, between the second substrate and the BEOL metallization stack, wherein the device layer comprises a pixel sensor region configured to sense incident radiation;

an opening extending through the first substrate, into the ILD layer, to expose the image sensor bond pad, wherein the opening is adjacent to a sidewall of the first substrate; and

a conductive layer lining the opening and the sidewall, wherein the conductive layer contacts the image sensor bond pad, and wherein the conductive layer extends continuously from the opening to the sidewall.