ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS

• US 20160163778A1
• Filed: 07/17/2015
• Published: 06/09/2016
• Est. Priority Date: 12/08/2014
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Chongqing Boe Optoelectronnics Technology Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Wang, Rui, SHANG, Fei, Wang, Wu, LI, Shaoru
• Granted Patent: US 9,905,626 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10K 2102/3026 Top emission
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

Embodiments of the present invention provide an array substrate, a display panel and a display apparatus. They relate to the technical field of display technologies and can prevent the peripheral signal wirings of a display region from occupying non-display regions on both sides additionally. In this way, when the array substrate is applied in the display panel, the frame on both sides of the display region on the display panel may be omitted. The array substrate includes: a base substrate; signal lines located in positions on the base substrate corresponding to a display region of the array substrate; a pattern layer, in which the signal lines are arranged; and signal line wirings located between the pattern layer and the base substrate, wherein the signal line wirings are configured to input signals into the signal lines.

Claims

1. An array substrate, comprising:

a base substrate;

signal lines located in positions on the base substrate corresponding to a display region of the array substrate;

a pattern layer, in which the signal lines are arranged; and

signal line wirings located between the pattern layer and the base substrate,

wherein the signal line wirings are configured to input signals into the signal lines.

2. The array substrate according to claim 1, wherein the signal lines comprise gate lines and the signal line wirings include gate line wirings,

wherein the gate line wirings are configured to input gate scanning signals into the gate lines.

3. The array substrate according to claim 2, wherein the pattern layer includes a first pattern layer in which the gate lines are arranged, and the array substrate further comprises:

a first insulation layer located between the first pattern layer and the base substrate, the gate line wirings being located between the first insulation layer and the base substrate,

wherein the first insulation layer is provided with first via holes therein, the first via holes being configured to connect the gate lines with the gate line wirings.

4. The array substrate according to claim 3, further comprising:

data lines arranged to cross with the gate lines;

a driving integrated circuit unit located in a first position on the base substrate corresponding to a non-display region of the array substrate and close to a first end of each of the data lines, the driving integrated circuit unit comprising a source driving circuit unit;

a GOA unit located in a second position on the base substrate corresponding to the non-display region of the array substrate and close to a second end of each of the data lines; and

gate line wiring connection lines arranged in the same layer as the gate line wirings, the gate line wiring connection lines being configured to connect the gate line wirings with the GOA unit.

5. The array substrate according to claim 4, further comprising:

gate scanning signal connection lines arranged in the same layer as the gate line wiring connection lines,

wherein the driving integrated circuit unit further comprises a GOA signal unit, the gate scanning signal connection lines being configured to connect the GOA unit with the GOA signal unit.

6. The array substrate according to claim 3, further comprising:

data lines arranged to cross with the gate lines;

a driving integrated circuit unit located in a position on the base substrate corresponding to a non-display region of the array substrate and close to any end of each of the data lines, the driving integrated circuit unit comprising a gate driving circuit unit and a source driving circuit unit; and

gate line wiring connection lines arranged in the same layer as the gate line wirings, the gate line wiring connection lines being configured to connect the gate line wirings with the gate driving circuit unit.

7. The array substrate according to claim 3, wherein the pattern layer further comprises a second pattern layer in which the gate line wirings are arranged, and the array substrate further comprises:

data lines arranged to cross with the gate lines, the data lines and the gate lines delimiting a plurality of pixel regions;

organic light emitting units arranged in the pixel regions and configured to emit light in a top emitting mode with respect to the base substrate;

a second insulation layer located between the second pattern layer and the base substrate; and

a GOA unit located between the second insulation layer and the base substrate, wherein the second insulation layer is provided with second via holes therein, the second via holes being configured to connect the GOA unit with the gate line wirings.

8. The array substrate according to claim 7, further comprising:

a driving integrated circuit unit located in a position on the base substrate corresponding to a non-display region of the array substrate and close to any end of each of the data lines, the driving integrated circuit unit comprising a source driving circuit unit and a GOA signal unit; and

gate scanning signal connection lines arranged in the same layer as the gate line wirings, the gate scanning signal connection lines being configured to connect the gate line wirings with the GOA signal unit.

9. The array substrate according to claim 1, wherein the signal lines are composed of metal simple substance and/or metal alloy material, and

wherein the signal line wirings are covered by the signal lines in a direction perpendicular to a plane surface of the base substrate.

10. The array substrate according to claim 4, wherein the gate line wiring connection lines are composed of metal simple substance and/or metal alloy material, and

wherein the gate line wiring connection lines are parallel to the data lines and the parts of the gate line wiring connection lines overlapped with the data lines are covered by the data lines in a direction perpendicular to a plane surface of the base substrate.

11. The array substrate according to claim 6, wherein the gate line wiring connection lines are composed of metal simple substance and/or metal alloy material, and

wherein the gate line wiring connection lines are parallel to the data lines and the parts of the gate line wiring connection lines overlapped with the data lines are covered by the data lines in a direction perpendicular to a plane surface of the base substrate.

12. The array substrate according to claim 5, wherein the gate scanning signal connection lines are composed of metal simple substance and/or metal alloy material, and

wherein the parts of the gate scanning signal connection lines overlapped with the data lines are covered by the data lines in a direction perpendicular to a plane surface of the base substrate.

13. The array substrate according to claim 8, wherein the gate scanning signal connection lines are composed of metal simple substance and/or metal alloy material, and

wherein the parts of the gate scanning signal connection lines overlapped with the data lines are covered by the data lines in a direction perpendicular to a plane surface of the base substrate.

14. The array substrate according to claim 4, further comprising:

data line leads configured to connect the data lines with the source driving circuit unit.

15. The array substrate according to claim 5, further comprising:

data line leads configured to connect the data lines with the source driving circuit unit.

16. The array substrate according to claim 6, further comprising:

data line leads configured to connect the data lines with the source driving circuit unit.

17. The array substrate according to claim 8, further comprising:

data lines lead configured to connect the data lines with the source driving circuit unit.

18. The array substrate according to claim 1, wherein the signal lines comprise data lines and the signal line wirings comprise data line wirings, and

wherein the data line leads are configured to input source driving signals into the data lines.

19. A display panel comprising an array substrate, the array substrate comprising:

a base substrate;

signal lines located in positions on the base substrate corresponding to a display region of the array substrate;

a pattern layer, in which the signal lines are arranged; and

signal line wirings located between the pattern layer and the base substrate,

wherein the signal line wirings are configured to input signals into the signal lines.

20. A display apparatus comprising a display panel, the display panel comprising:

an array substrate, the array substrate comprising;

a base substrate;

signal lines located in positions on the base substrate corresponding to a display region of the array substrate;

a pattern layer, in which the signal lines are arranged; and

signal line wirings located between the pattern layer and the base substrate,

wherein the signal line wirings are configured to input signals into the signal lines.