MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
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Abstract
A transistor using an oxide semiconductor, which has good on-state characteristics is provided. A high-performance semiconductor device including the transistor capable of high-speed response and high-speed operation is provided. The transistor includes the oxide semiconductor film including a channel formation region and low-resistance regions in which a metal element and a dopant are included. The channel formation region is positioned between the low-resistance regions in the channel length direction. In a manufacturing method of the transistor, the metal element is added by heat treatment performed in the state where the oxide semiconductor film is in contact with a film including the metal element and the dopant is added through the film including the metal element by an implantation method so that the low resistance regions in which a metal element and a dopant are included are formed.
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Citations
15 Claims
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1. (canceled)
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2. A semiconductor device comprising:
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an oxide semiconductor layer comprising a first region, a second region, and a third region; a gate electrode layer over the oxide semiconductor layer; and a side wall insulator on a side surface of the gate electrode layer, wherein the second region is between the first region and the third region, wherein the first region comprises a channel formation region, wherein the channel formation region and the gate electrode layer overlap each other, wherein the side wall insulator and the second region overlap each other, wherein the second region comprises argon, wherein the third region comprises argon and titanium, wherein a resistance of the second region is lower than a resistance of the first region, and wherein a resistance of the third region is lower than the resistance of the second region. - View Dependent Claims (3, 4, 5, 6, 7, 8)
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9. A semiconductor device comprising:
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an oxide semiconductor layer comprising a first region, a second region, and a third region; a gate electrode layer over the oxide semiconductor layer; a side wall insulator on a side surface of the gate electrode layer; a source electrode layer; and a drain electrode layer, wherein the second region is between the first region and the third region, wherein the first region comprises a channel formation region, wherein the channel formation region and the gate electrode layer overlap each other, wherein the side wall insulator and the second region overlap each other, wherein the source electrode layer and the drain electrode layer are in contact with the third region, wherein the second region comprises argon, wherein the third region comprises argon and titanium, wherein a resistance of the second region is lower than a resistance of the first region, and wherein a resistance of the third region is lower than the resistance of the second region. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification