SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

• US 20160163876A1
• Filed: 12/04/2014
• Published: 06/09/2016
• Est. Priority Date: 12/04/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WU, Chang-Ming, HUANG, Wei-Hang, LIU, Shih-Chang
• Granted Patent: US 9,397,228 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The semiconductor device structure includes a second gate stack over the semiconductor substrate. The semiconductor device structure includes an erase gate between the first gate stack and the second gate stack. The erase gate has a recess recessed toward the semiconductor substrate. The semiconductor device structure includes a first word line adjacent to the first gate stack. The semiconductor device structure includes a second word line adjacent to the second gate stack.

Claims

1. A semiconductor device structure, comprising:

a semiconductor substrate;

a first gate stack over the semiconductor substrate;

a second gate stack over the semiconductor substrate;

an erase gate between the first gate stack and the second gate stack, wherein the erase gate has a recess recessed toward the semiconductor substrate;

a first word line adjacent to the first gate stack;

a second word line adjacent to the second gate stack;

a first spacer over a top surface of the erase gate; and

a second spacer over the top surface of the erase gate, wherein the first spacer and the second spacer are separated from each other.

2. The semiconductor device structure as claimed in claim 1, wherein the first gate stack comprises a first floating gate and a first control gate over the first floating gate, and the second gate stack comprises a second floating gate and a second control gate over the second floating gate.

3. The semiconductor device structure as claimed in claim 1, wherein the first spacer is over a first sidewall of the first gate stack, and the second spacer is over a second sidewall of the second gate stack.

4. The semiconductor device structure as claimed in claim 1, further comprising:

a metal silicide layer over the erase gate and between the first spacer and the second spacer, wherein the metal silicide layer is in direct contact with the first spacer and the second spacer.

5. The semiconductor device structure as claimed in claim 1, further comprising:

a contact structure over the erase gate and between the first spacer and the second spacer, wherein the contact structure is electrically connected to the erase gate.

6. The semiconductor device structure as claimed in claim 1, further comprising:

a third spacer between the first word line and the first gate stack; and

a fourth spacer between the second word line and the second gate stack.

7. The semiconductor device structure as claimed in claim 1, wherein the recess is a curved recess.

8. The semiconductor device structure as claimed in claim 1, wherein the semiconductor substrate has a first doped region, a second doped region, and a third doped region, the erase gate is over the first doped region, the first word line is between the second doped region and the first gate stack, and the second word line is between the third doped region and the second gate stack.

21. The semiconductor device structure as claimed in claim 6, wherein the first spacer is an ONO (oxide/nitride/oxide) layer, and the second spacer is an ONO layer.

22. The semiconductor device structure as claimed in claim 1, wherein the first word line has a first width and the second word line has a second width, and a difference between the first width and the second width ranges from 1 to 10 Å

.

23. The semiconductor device structure as claimed in claim 22, wherein a ratio of the difference between the first width and the second width to the first width ranges from 0.001 to 0.05.

24. The semiconductor device structure as claimed in claim 1, wherein the erase gate, the first word line, and the second word line comprise a same material.

25. The semiconductor device structure as claimed in claim 1, further comprising:

a third spacer over a first sidewall of the first word line; and

a fourth spacer over a second sidewall of the second word line, wherein the first spacer, the second spacer, the third spacer, and the fourth spacer comprise a same material.

9. A semiconductor device structure, comprising:

a semiconductor substrate;

a first gate stack over the semiconductor substrate;

a second gate stack over the semiconductor substrate;

an erase gate between the first gate stack and the second gate stack, wherein the erase gate has a recess recessed toward the semiconductor substrate;

a first spacer over the erase gate and adjacent to the first gate stack;

a second spacer over the erase gate and adjacent to the second gate stack, wherein a first portion of the first spacer and a second portion of the second spacer are in the recess;

a first word line adjacent to the first gate stack; and

a second word line adjacent to the second gate stack.

10. The semiconductor device structure as claimed in claim 9, wherein the first gate stack comprises a first floating gate and a first control gate over the first floating gate, and the second gate stack comprises a second floating gate and a second control gate over the second floating gate.

11. The semiconductor device structure as claimed in claim 9, further comprising:

a third spacer between the first word line and the first gate stack; and

a fourth spacer between the second word line and the second gate stack.

12. The semiconductor device structure as claimed in claim 9, wherein the first gate stack, the erase gate, and the second gate stack are between the first word line and the second word line.

13. The semiconductor device structure as claimed in claim 9, further comprising:

a contact structure over the erase gate and between the first spacer and the second spacer, wherein the contact structure is electrically connected to the erase gate.

14. The semiconductor device structure as claimed in claim 9, wherein the erase gate, the first word line, and the second word line comprise a same material.

15. The semiconductor device structure as claimed in claim 9, further comprising:

a third spacer over a first sidewall of the first word line; and

a fourth spacer over a second sidewall of the second word line, wherein the first spacer, the second spacer, the third spacer, and the fourth spacer comprise a same material.

16-20. -20. (canceled)