MEMS-BASED WAFER LEVEL PACKAGING FOR THERMO-ELECTRIC IR DETECTORS

• US 20160163942A1
• Filed: 12/03/2015
• Published: 06/09/2016
• Est. Priority Date: 12/04/2014
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Emadi, Arvin, Kerness, Nicole D., Samoilov, Arkadii V., Sahasrabudhe, Abhishek
• Granted Patent: US 10,439,118 B2
• Time in Patent Office: Days
• CPC Class Codes: G01J 5/0225 Shape of the cavity itself or of elements contained in or suspended over the cavity
• CPC Class Codes: G01J 5/024 Special manufacturing steps or sacrificial layers or layer structures
• CPC Class Codes: G01J 5/12 using thermoelectric elements, e.g. thermocouples
• CPC Class Codes: H01L 27/14649 Infrared imagers
• CPC Class Codes: H10N 10/80 Constructional details
• CPC Class Codes: H10N 10/851 comprising inorganic compositions
• CPC Class Codes: H10N 10/854 comprising only metals H10N10/852, H10N10/853 take precedence

Abstract

A device and techniques for fabricating the device are described for forming a wafer-level thermal sensor package using microelectromechanical system (MEMS) processes. In one or more implementations, a wafer level thermal sensor package includes a thermopile stack, which includes a substrate, a dielectric membrane, a first thermoelectric layer, a first interlayer dielectric, a second thermoelectric layer, a second interlayer dielectric, a metal connection assembly, a passivation layer, where the passivation layer includes at least one of a trench or a hole, and where the substrate includes a cavity adjacent to the at least one trench or hole, and a bond pad disposed on the passivation layer and electrically coupled to the metal connection assembly; and a cap wafer assembly coupled to the thermopile stack, the cap wafer assembly including a wafer having a cavity formed on a side of the wafer configured to be adjacent to the thermopile stack.

Claims

1. A wafer level thermal sensor package, comprising:

a thermopile stack, including

a substrate;

a dielectric membrane formed on a first side of the substrate;

a first thermoelectric layer formed on the dielectric membrane;

a first interlayer dielectric formed on the first thermoelectric layer and the dielectric membrane;

a second thermoelectric layer formed on the first interlayer dielectric;

a second interlayer dielectric formed on the second thermoelectric layer and the first interlayer dielectric;

a metal connection assembly electrically coupled to the first thermoelectric layer and the second thermoelectric layer;

a passivation layer disposed on the metal connection assembly and the second interlayer dielectric, where the passivation layer includes at least one of a trench or a hole, and where the substrate includes a cavity adjacent to the at least one trench or hole; and

a bond pad disposed on the passivation layer and electrically coupled to the metal connection assembly; and

a cap wafer assembly coupled to the thermopile stack, the cap wafer assembly including a wafer having a cavity formed on a side of the wafer configured to be adjacent to the thermopile stack.

2. The wafer level thermal sensor in claim 1, where the substrate includes a silicon wafer.

3. The wafer level thermal sensor in claim 1, where the substrate includes a sacrificial layer disposed adjacent to the dielectric membrane.

4. The wafer level thermal sensor in claim 1, where at least one of the first thermoelectric layer or the second thermoelectric layer includes at least one of n-doped silicon, p-doped silicon, or a metal.

5. The wafer level thermal sensor in claim 1, where the first thermoelectric layer and the second thermoelectric layer form a thermopile.

6. The wafer level thermal sensor in claim 1, where the passivation layer includes an absorption stack.

7. The wafer level thermal sensor in claim 1, where the cap wafer assembly includes a metal layer on at least one surface of the wafer.

8. The wafer level thermal sensor in claim 7, where the metal layer includes at least one of aluminum, gold, nickel, tantalum, or titanium.

9. The wafer level thermal sensor in claim 1, where the cap wafer assembly includes an optical filter on at least one surface of the wafer.

10. The wafer level thermal sensor in claim 9, where the optical filter includes at least one of germanium, silicon, zinc sulfide, zinc selenide, or yttrium fluoride.

11. The wafer level thermal sensor in claim 1, where the cap wafer assembly includes a silicon wafer.

12. The wafer level thermal sensor in claim 1, where the cap wafer assembly includes a metal stack configured to bond the cap wafer assembly to the thermopile stack.

13. The wafer level thermal sensor in claim 1, where the cap wafer assembly includes a lens.

14. The wafer level thermal sensor in claim 1, further including a second cap wafer coupled to the thermopile stack and the substrate, where the second cap wafer is coupled to a side of the substrate that is distal from the thermopile stack.

15. The wafer level thermal sensor in claim 1, further including a printed circuit board coupled to the wafer level thermal sensor.

16. A wafer level thermal sensor package, comprising:

a base including a stepped structure;

a substrate disposed on the stepped structure, where the base, the stepped structure, and the substrate define a first cavity that reduces a thermal gradient;

a first thermopile disposed on the substrate;

a second thermopile disposed on the substrate;

a resistance temperature detector disposed on the substrate; and

a cap wafer assembly coupled to the base, where the cap wafer assembly, the base, and the substrate define a second cavity that houses the first thermopile, the second thermopile, and the resistance temperature detector.

17. The wafer level thermal sensor package in claim 16, where the first cavity includes at least one of a vacuum or a low-conductive gas.

18. A process for fabricating a wafer level thermal sensor, comprising:

forming a thermopile stack on a substrate, where the thermopile stack includes

a substrate;

a dielectric membrane formed on a first side of the substrate;

a first thermoelectric layer formed on the dielectric membrane;

a first interlayer dielectric formed on the first thermoelectric layer and the dielectric membrane;

a second thermoelectric layer formed on the first interlayer dielectric;

a second interlayer dielectric formed on the second thermoelectric layer and the first interlayer dielectric;

a metal connection assembly electrically coupled to the first thermoelectric layer and the second thermoelectric layer;

a passivation layer disposed on the metal connection assembly and the second interlayer dielectric, where the passivation layer includes at least one of a trench or a hole, and where the substrate includes a cavity adjacent to the at least one trench or hole; and

a bond pad disposed on the passivation layer and electrically coupled to the metal connection assembly; and

placing a cap wafer on the thermopile stack.

19. The process for fabricating a wafer level thermal sensor in claim 18, where the wafer level thermal sensor includes a through-silicon via.

20. The process for fabricating a wafer level thermal sensor in claim 18, further comprising:

placing a second cap wafer on a side of the substrate distal from the thermopile stack.