Amplifier Dynamic Bias Adjustment for Envelope Tracking
First Claim
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1. A circuital arrangement comprising:
- an amplifier comprising;
stacked transistors having a plurality of gate terminals configured to operatively provide a plurality of dynamic bias voltages or currents to the stacked transistors;
an input port operatively connected to a gate terminal of an input transistor of the stacked transistors configured to receive a radio frequency (RF) signal;
an output port operatively connected to an output transistor of the stacked transistors configured to output an amplified version of the RF signal; and
a reference terminal operatively coupling the input transistor to a reference potential, wherein the stacked transistors comprise two subsets of transistors operatively arranged in series;
a) a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal; and
b) a second subset comprising;
i) one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to a drain terminal of the output transistor; and
ii) one or more gate capacitors connected between gate terminals of the one or more transistors of the second subset and the reference potential, wherein a gate capacitor of the one or more gate capacitors is configured to allow a gate voltage at a gate terminal of a transistor of the one or more transistors of the second subset to vary along with a radio frequency (RF) voltage at a drain of the transistor.
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Abstract
An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor.
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Citations
43 Claims
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1. A circuital arrangement comprising:
an amplifier comprising; stacked transistors having a plurality of gate terminals configured to operatively provide a plurality of dynamic bias voltages or currents to the stacked transistors; an input port operatively connected to a gate terminal of an input transistor of the stacked transistors configured to receive a radio frequency (RF) signal; an output port operatively connected to an output transistor of the stacked transistors configured to output an amplified version of the RF signal; and a reference terminal operatively coupling the input transistor to a reference potential, wherein the stacked transistors comprise two subsets of transistors operatively arranged in series; a) a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal; and b) a second subset comprising; i) one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to a drain terminal of the output transistor; and ii) one or more gate capacitors connected between gate terminals of the one or more transistors of the second subset and the reference potential, wherein a gate capacitor of the one or more gate capacitors is configured to allow a gate voltage at a gate terminal of a transistor of the one or more transistors of the second subset to vary along with a radio frequency (RF) voltage at a drain of the transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. A method of amplifying a radio frequency (RF) signal in a circuital arrangement, the method comprising:
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providing an amplifier comprising stacked transistors in a cascode configuration; connecting, for all transistors of the stacked transistors with the exception of an input transistor of the stacked transistors, gate capacitors between gate terminals of corresponding transistors of the stacked transistors and a reference potential; adapting the arrangement to operatively connect a plurality of bias supplies to a plurality of gate terminals of the stacked transistors and to a drain terminal of an output transistor of the stacked transistors; applying an input RF signal to an input port of the arrangement operatively connected to an input transistor of the stacked transistors; varying a bias supply of the plurality of bias supplies operatively connected to the drain of the output transistor, and impressing a desired amplification on the input RF signal to obtain an amplified output RF signal by varying at least one bias supply of the plurality of bias supplies operatively connected to a gate terminal of one transistor of the stacked transistors, wherein each of the gate capacitors is configured to allow a voltage at a gate of a corresponding transistor to vary along with an RF voltage at a drain of the corresponding transistor. - View Dependent Claims (41, 42, 43)
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Specification