Systems and Methods For Efficient Handling of Data Traffic and Processing Within a Processing Device

• US 20160164807A1
• Filed: 02/16/2016
• Published: 06/09/2016
• Est. Priority Date: 07/11/2007
• Status: Abandoned Application

• Current Assignee: Commex Technologies, Ltd.
• Original Assignee: Commex Technologies, Ltd.
• Inventors: Engel, Yehiel, Ganor, Avraham, Horowitz, Tal, Schnarch, Michael Chaim, Shachar, Yaron, Weiser, Uri Chanan
• Application Number:
  US15/044,688
• Publication Number:
  US 20160164807A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: H04L 49/40 Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04L 49/70 Virtual switches
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention provides an improved platform hub that aims to, in some embodiments, optimize system resources to improve system performance and/or reduce consumption of power.

Claims

1. A processing device, comprising:

a housing;

a chip housed in the housing;

a first processing agent housed in the housing and connected to the chip; and

a network interface operable to connect the processing device to an external network that is external to the housing, wherein

the chip comprises;

an interconnect;

a second processing agent communicatively connected to the interconnect, the second processing agent comprising a plurality of general purpose processor cores and a cache memory; and

a network adapter communicatively connected to the interconnect and to the network interface, the network adapter being operable to receive and classify packets received from the network interface, wherein

the network adapter is configured such that, in response to receiving a particular packet, the network adapter uses the interconnect to store a payload portion of the packet in the cache memory of the second processing agent.

2. The processing device of claim 1, wherein the network adapter is configured such that, in response to receiving via the network interface a packet having a header and a data payload, the network adapter i) compares data from both the data payload and header with pre-determined data, and ii) performs a certain predetermined action in response to determining that the compared data matches the predetermined data.

3. The processing device of claim 2, wherein the network adapter comprises a packet parser and an action engine communicatively connected to the packet parser, wherein the action engine is operable to receive from the packet parser packet data and/or commands, and the action engine is further operable to do one or more of (i) perform a packet filtering operation on packets parsed by the packet parser and (ii) perform a packet modification operation on packets parsed by the packet parser.

4. The processing device of claim 1, wherein the chip further comprises an accelerating agent communicatively connected to the interconnect, the accelerating agent being adapted to perform acceleration operations.

5. The processing device of claim 4, wherein

the accelerating agent is a cryptographic accelerating agent, and

the second processing agent is adapted to use the interconnect to provide to the cryptographic accelerating agent i) the payload and ii) a command identifying a cryptographic operation that the cryptographic accelerating agent should perform on the payload.

6. The processing device of claim 5, wherein the cryptographic accelerating agent comprises a direct memory access (DMA) engine coupled to the interconnect, and the DMA engine is configured to i) receive the payload provided by the second processing agent and ii) write the payload into a memory space of the cryptographic agent.

7. A chip for use in a network server comprising a first processing agent and a network interface, said chip comprising:

an interconnect;

a second processing agent communicatively connected to the interconnect, the second processing agent comprising a plurality of general purpose processor cores and a cache memory;

a network adapter communicatively connected to the interconnect and to the network interface, the network adapter being operable to receive and classify packets received from the network interface; and

an accelerating agent communicatively connected to the interconnect, the accelerating agent being adapted to perform acceleration operations.

8. The chip of claim 7, wherein the network adapter is configured such that, in response to receiving via the network interface a packet having a header and a data payload, the network adapter i) compares data from both the data payload and header with pre-determined data, and ii) performs a certain predetermined action in response to determining that the compared data matches the predetermined data.

9. The chip of claim 8, wherein the network adapter comprises a packet parser and an action engine communicatively connected to the packet parser, wherein the action engine is operable to receive from the packet parser packet data and/or commands, and the action engine is further operable to do one or more of (i) perform a packet filtering operation on packets parsed by the packet parser and (ii) perform a packet modification operation on packets parsed by the packet parser.

10. The chip of claim 7, wherein the network adapter comprises a packet parser, an action engine, and an identifier module operable to receive packet information from the packet parser and, based on the packet information and configuration data, provide a command to the action engine.

11. The chip of claim 7, wherein the network adapter is operable to determine a flow to which a packet received from the network interface.

12. The chip of claim 11, wherein the network adapter is operable to determine whether a received packet meets specified criteria and is operable to drop the received packet in response to determining that the packet meets the specified criteria.

13. The chip of claim 11, wherein acceleration agent is a cryptographic acceleration agent.

14. The chip of claim 7, wherein the network adapter is further operable, such that, in response to receiving a packet from the network interface, the network adapter is operable to determine whether the received packet comprise a Transmission Control Protocol (TCP) protocol data unit (PDU).

15. A chip for use in a processing device, said chip comprising:

an interconnect;

a first processor communicatively connected to the interconnect and communicatively connected to a network interface, the first processor being operable to receive packets via the network interface; and

a second processor communicatively connected to the interconnect, the second processor comprising a plurality of processor cores and cache memory, wherein

the first processor is configured to;

parse a packet received via the network interface and perform one or more actions based on information contained in the received packet, wherein said actions include providing at least a portion of the received packet to the cache memory of the second processor via the interconnect.

16. The chip of claim 15, wherein the cache memory comprises a plurality of L2 caches.

17. The chip of claim 15, wherein the first processor comprises:

a packet parser configured to parse packets provided to the first processor from a communication agent and to extract one or more fields from the packets; and

a configurable action engine operable to (a) receive one or more packet fields extracted by the packet parser and (b) perform one or more actions based on information contained in the received one or more packet fields, wherein said actions include providing a received packet to the second processor via the interconnect.

18. The chip of claim 17, wherein the action engine is operable to perform packet filtering of the packets received from the communication agent.

19. The chip of claim 15, further comprising:

an accelerating agent configured to perform a cryptographic function, the accelerating agent being communicatively connected to the second processor through the interconnect.

20. The chip of claim 15, wherein the first processor is operable to determine whether a packet received via the network interface meets specified criteria and is operable to drop the packet in response to determining that the packet meets the specified criteria.