CIRCUIT DESIGN LAYOUT IN MULTIPLE SYNCHRONOUS REPRESENTATIONS

• US 20160171143A1
• Filed: 12/11/2014
• Published: 06/16/2016
• Est. Priority Date: 12/11/2014
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Smith, Edwin, Suiter, Gerald, Potts, Henry
• Granted Patent: US 10,127,343 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/1652 the display being flexible, e.g. mimicking a sheet of paper, or rollable
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 2115/12 Printed circuit boards [PCB] or multi-chip modules [MCM]
• CPC Class Codes: G06F 2203/0338 Fingerprint track pad, i.e. fingerprint sensor used as pointing device tracking the fingertip image
• CPC Class Codes: G06F 3/023 Arrangements for converting discrete items of information into a coded form, e.g. arrangements for interpreting keyboard generated codes as alphanumeric codes, operand codes or instruction codes
• CPC Class Codes: G06F 3/04842 Selection of displayed objects or displayed text elements G06F3/0482 takes precedence
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 3/46 Manufacturing multilayer circuits

Abstract

This application discloses a computing system implementing tools and mechanisms to synchronize multiple layouts for a circuit design during the layout process. The tools and mechanisms can implement multiple communicating kernels, each to manage at least one of the layouts. In response to an alteration of one of the layouts, the kernels can communicate with each other, so that the kernel corresponding to the unaltered layout can automatically augment corresponding layouts for the circuit design to synchronize with the altered layout. At least one of the layouts can include a 3-dimensional layout representation of the circuit design, the tools and mechanisms can perform 3-dimensional design rule checking based on mechanical constraints and 3-dimensional solid component models in response to alterations to a 2-dimensional layout representation of the circuit design.

Claims

1. A method comprising:

altering, by a computing system, a first layout representation for a circuit design in response to user input; and

automatically augmenting, by the computing system, a second layout representation for the circuit design in response to the alteration of the first layout representation, which synchronizes the second layout representation with the first layout representation.

2. The method of claim 1, wherein altering the first layout representation for the circuit design is performed by a first kernel of the computing system, and automatically augmenting the second layout representation for the circuit design is performed by a second kernel of the computing system.

3. The method of claim 1, wherein one of the first or second layout representations corresponds to a 2.5-dimensional data model of the circuit design, and the other of the first or second layout representations corresponds to a 3-dimensional data model of the circuit design.

4. The method of claim 1, wherein one of the first or second layout representations corresponds to a 2.5-dimensional graphical presentation of the circuit design, and the other of the first or second layout representations corresponds to a 3-dimensional graphical presentation of the circuit design.

5. The method of claim 1 further comprises generating, by a computing system, a first data model corresponding to the first layout representation for the circuit design by replicating a second data model corresponding to the second layout representation for the circuit design and augmenting the replica of the second data model with component models associated with the first layout representation for the circuit design.

6. The method of claim 1 further comprises automatically performing, by the computing system, at least one design rule check to compare the second layout representation with electro-mechanical constraints in response to the alteration of the first layout representation.

7. The method of claim 1 further comprises presenting, by the computing system, at least one of the first and second layout representations of the circuit design in a graphical display.

8. A system comprising:

a memory device configured to store machine-readable instructions; and

a computing system including one or more processing devices, in response to executing the machine-readable instructions, configured to alter a first layout representation for a circuit design in response to user input, and augment a second layout representation for the circuit design in response to the alteration of the first layout representation, which synchronizes the second layout representation with the first layout representation.

9. The system of claim 8, wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to implement a first kernel to alter the first layout representation for the circuit design.

10. The system of claim 9, wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to implement a second kernel to augment the second layout representation for the circuit design.

11. The system of claim 8, wherein one of the first or second layout representations corresponds to a 2.5-dimensional data model of the circuit design, and the other of the first or second layout representations corresponds to a 3-dimensional data model of the circuit design.

12. The system of claim 8, wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to perform at least one design rule check to compare the second layout representation with electro-mechanical constraints in response to the alteration of the first layout representation.

13. The system of claim 12, wherein the electro-mechanical constraints include at least one of a description an enclosure for an electronic device defined by the circuit design, fasteners to affix the electronic device defined by the circuit design to the enclosure, an addition electronic device to be coupled to the electronic device defined by the circuit design, or one or more heat dissipation devices to be coupled to the electronic device defined by the circuit design.

14. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

altering a first layout representation for a circuit design in response to user input; and

augmenting a second layout representation for the circuit design in response to the alteration of the first layout representation, which synchronizes the second layout representation with the first layout representation.

15. The apparatus of claim 14, wherein the one or more processing devices, in response to the instructions, are configured to implement a first kernel to alter the first layout representation for the circuit design and to implement a second kernel to augment the second layout representation for the circuit design.

16. The apparatus of claim 14, wherein one of the first or second layout representations corresponds to a 2.5-dimensional data model of the circuit design, and the other of the first or second layout representations corresponds to a 3-dimensional data model of the circuit design.

17. The apparatus of claim 14, wherein one of the first or second layout representations corresponds to a 2.5-dimensional graphical presentation of the circuit design, and the other of the first or second layout representations corresponds to a 3-dimensional graphical presentation of the circuit design.

18. The apparatus of claim 14, wherein the instructions configured to cause the one or more processing devices to perform operations further comprising generating a first data model corresponding to the first layout representation for the circuit design by replicating a second data model corresponding to the second layout representation for the circuit design and augmenting the replica of the second data model with component models associated with the first layout representation for the circuit design.

19. The apparatus of claim 14, wherein the instructions configured to cause the one or more processing devices to perform operations further comprising performing at least one design rule check to compare the second layout representation with electro-mechanical constraints in response to the alteration of the first layout representation.

20. The apparatus of claim 14, wherein the instructions configured to cause the one or more processing devices to perform operations further comprising presenting at least one of the first and second layout representations of the circuit design in a graphical display.