THREE DIMENSIONAL MEMORY DEVICE WITH BLOCKING DIELECTRIC HAVING ENHANCED PROTECTION AGAINST FLUORINE ATTACK

• US 20160172366A1
• Filed: 06/26/2015
• Published: 06/16/2016
• Est. Priority Date: 12/16/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: PERI, Somesh, MATAMIS, George, KOKA, Sateesh, MAKALA, Raghuveer S., SHARANGPANI, Rahul, LEE, Yao-Sheng, ZHAO, Wei
• Granted Patent: US 9,515,079 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02332 into an oxide layer, e.g. changing SiO to SiON
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02356 treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Blocking dielectric structures and/or thicker barrier metal films for preventing or reducing fluorine diffusion are provided. A blocking dielectric layer can be formed as an outer layer of a memory film in a memory stack structure extending through electrically insulating layers and sacrificial material layers. After formation of backside recesses by removal of the sacrificial material layers, dopants can be introduced into physically exposed portions of the blocking dielectric layer, for example, by plasma treatment or thermal treatment, to form silicon oxynitride regions which can reduce or prevent fluorine diffusion. Alternatively or additionally, a set of metal oxide blocking dielectric material portions can be formed in the backside recesses to retard or prevent fluorine diffusion. To minimize adverse impact on the electrically conductive layers formed in the backside recesses, the blocking dielectric material portions can be laterally recessed from a trench employed to form the backside recesses.

Claims

1. A monolithic three-dimensional memory device comprising:

a stack of alternating layers comprising insulating layers and electrically conductive layers and located over a substrate;

a memory opening extending vertically through the stack; and

a memory film and a semiconductor channel located within the memory opening, the memory film comprising a blocking dielectric which comprises an alternating stack of silicon oxide portions and silicon oxynitride portions.

2. The monolithic three-dimensional memory device of claim 1, wherein:

the silicon oxide portions are located at same levels as respective insulating layers in the stack; and

the silicon oxynitride portions are located at same levels as the electrically conductive layers in the stack.

3. The monolithic three-dimensional memory device of claim 2, wherein:

an atomic concentration of nitrogen in the blocking dielectric decreases as a function of distance from the electrically conductive layers in portions of the blocking dielectric; and

an atomic concentration of oxygen atoms in the blocking dielectric increases as a function of distance from the electrically conductive layers in portions of the blocking dielectric.

4. The monolithic three-dimensional memory device of claim 1, wherein the blocking dielectric has a same thickness throughout its height, and wherein a compositional gradient is present in regions of the silicon oxide portions that adjoin the insulating layers.

5. The monolithic three-dimensional memory device of claim 1, wherein:

each insulating layer comprises an inner silicon oxide layer covered by a respective outer silicon oxynitride layer;

the outer silicon oxynitride layer and the silicon oxynitride portions together form a continuous silicon oxynitride region;

the silicon oxynitride portions form first vertical portions of the continuous silicon oxynitride region;

the outer silicon oxynitride layers form second vertical portions and horizontal portions of the continuous silicon oxynitride region; and

each horizontal portion connects a pair of adjacent, laterally offset first and second vertical portions.

6. The monolithic three-dimensional memory device of claim 5, further comprising:

a set of metal oxide blocking dielectric material portions interposed between the memory film and each of the electrically conductive layers, wherein each of the metal oxide blocking dielectric material portions comprises;

a vertical portion contacting a sidewall of a respective electrically conductive layer and a sidewall respective silicon oxynitride portion;

a top horizontal portion extending outward from the memory opening and contacting a top surface of the respective electrically conductive layer and a bottom surface of a respective silicon oxynitride layer; and

a bottom horizontal portion extending outward from the memory opening and contacting a bottom surface of the respective electrically conductive layer and a top surface of another respective silicon oxynitride layer.

7. The monolithic three-dimensional memory device of claim 1, wherein:

the monolithic three-dimensional memory device comprises a vertical NAND device located over the substrate;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;

the substrate comprises a silicon substrate;

the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

8. A monolithic three-dimensional memory device comprising:

a stack of alternating layers comprising insulating layers and electrically conductive layers and located over a substrate;

a first memory opening extending vertically through the stack;

a first memory film and a first semiconductor channel located within the first memory opening; and

a set of metal oxide blocking dielectric material portions interposed between the first memory film and each of the electrically conductive layers, wherein each of the metal oxide blocking dielectric material portions in the set comprises;

a vertical portion contacting a sidewall of a respective electrically conductive layer;

a top horizontal portion extending outward from the first memory opening and contacting only a portion of a top surface of the respective electrically conductive layer; and

a bottom horizontal portion extending outward from the first memory opening and contacting only a portion of a bottom surface of the respective electrically conductive layer.

9. The monolithic three-dimensional memory device of claim 8, wherein:

a top surface of the top horizontal portion is coplanar with a topmost surface of the respective electrically conductive layer;

a bottom surface of the bottom horizontal portion is coplanar with a bottommost surface of the respective electrically conductive layer; and

the set of metal oxide blocking dielectric material portions comprises polycrystalline aluminum oxide material.

10. The monolithic three-dimensional memory device of claim 8, further comprising:

a trench extending through the stack of alternating layers;

an insulating spacer located at a periphery of the trench; and

a contact via structure contacting a portion of the substrate and located within the insulating spacer;

wherein each metal oxide blocking dielectric material portion within the set is laterally spaced from the trench by a same lateral distance.

11. The monolithic three-dimensional memory device of claim 10, further comprising:

a second memory opening extending vertically through the stack and laterally spaced from the trench by a different distance than the first memory opening is from the trench; and

a second memory film and a second semiconductor channel located within the second memory opening.

12. The monolithic three-dimensional memory device of claim 8, wherein:

the first memory film further comprises a blocking dielectric extending through the stack of alternating layers;

the blocking dielectric comprises an alternating stack of silicon oxide portions and silicon oxynitride portions;

the silicon oxide portions contact respective insulating layers; and

the silicon oxynitride portions contact respective metal oxide blocking dielectric material portions.

13. The monolithic three-dimensional memory device of claim 8, wherein:

the monolithic three-dimensional memory device comprises a vertical NAND device located over the substrate;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;

the substrate comprises a silicon substrate;

the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

14. A method of forming a monolithic three-dimensional memory device, comprising:

forming a stack of alternating layers comprising first material layers and second material layers over a substrate;

forming memory openings through the stack of alternating layers;

forming memory stack structures in the memory openings, wherein each memory stack structure comprises a memory film and a semiconductor channel contacting an inner sidewall of the memory film, and the memory film comprises a silicon oxide blocking dielectric layer contacting a sidewall of a respective memory opening;

forming a trench extending through the stack of alternating layers;

forming backside recesses by removing the second material layers selective to the first material layers; and

doping with nitrogen portions of the silicon oxide blocking dielectric layer exposed in the backside recesses to form silicon oxynitride portions in the silicon oxide blocking dielectric layer.

15. The method of claim 14, wherein:

doping with nitrogen comprises using plasma or thermal doping;

the blocking dielectric layer comprises silicon oxide having a homogeneous composition and uniform thickness prior to the plasma doping; and

the blocking dielectric layer comprises an alternating stack of silicon oxide portions and silicon oxynitride portions after the plasma or thermal doping.

16. The method of claim 15, further comprising densifying using an in-situ steam generation (ISSG) anneal and doping with nitrogen exposed outer portions of the insulating layers in the stack of alternating layers such that each insulating layer comprises an inner densified silicon oxide layer covered by a respective outer silicon oxynitride layer, and the outer silicon oxynitride layer and the silicon oxynitride portions together form a continuous silicon oxynitride region.

17. The method of claim 14, further comprising forming electrically conductive layers in the backside recesses by depositing a conductive material, wherein an atomic concentration of nitrogen atoms in the silicon oxynitride portions of the blocking dielectric layer decreases as a function of distance from the electrically conductive layers.

18. The method of claim 14, further comprising:

forming a set of metal blocking dielectric material portions on the memory films within regions of the backside recesses that are adjacent to the memory films; and

filling the backside recesses with electrically conductive layers,

wherein each of the metal oxide blocking dielectric material portions comprises;

a vertical portion contacting a sidewall of a respective electrically conductive layer;

a top horizontal portion extending outward from the memory opening and contacting a top surface of the respective electrically conductive layer; and

a bottom horizontal portion extending outward from the memory opening and contacting a bottom surface of the respective electrically conductive layer.

19. The method of claim 14, wherein:

the monolithic three-dimensional memory device comprises a vertical NAND device located over the substrate;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;

the substrate comprises a silicon substrate;

the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

20. A method of forming a monolithic three-dimensional memory device, comprising:

forming a stack of alternating layers comprising first material layers and second material layers over a substrate;

forming memory openings through the stack of alternating layers;

forming memory stack structures in the memory openings;

forming a trench extending through the stack of alternating layers;

forming backside recesses by removing the second material layers selective to the first material layers;

forming a set of blocking dielectric material portions on the memory films within regions of the backside recesses that are adjacent to the memory films, each blocking dielectric material portion being laterally spaced from a sidewall of the trench; and

filling the backside recesses with electrically conductive layers.

21. The method of claim 20, wherein each of the blocking dielectric material portions comprises:

a vertical portion contacting a sidewall of a respective electrically conductive layer;

a top horizontal portion extending outward from the memory opening and contacting only a portion of a top surface of the respective electrically conductive layer; and

a bottom horizontal portion extending outward from the memory opening and contacting only a portion of a bottom surface of the respective electrically conductive layer.

22. The method of claim 21, wherein the set of metal oxide blocking dielectric material portions is formed by:

depositing a backside metal oxide blocking dielectric layer in the backside recesses and on sidewalls of the memory films;

filling the backside recesses with a sacrificial fill material layer;

laterally recessing the sacrificial fill material layer from a sidewall of the trench; and

removing physically exposed portions of the metal oxide backside blocking dielectric layer, wherein remaining portions of the metal oxide backside blocking dielectric layer constitute the set of metal oxide blocking dielectric material portions.

23. The method of claim 22, wherein the metal oxide backside blocking dielectric layer is deposited as an amorphous aluminum oxide material, and the method further comprises:

converting the aluminum oxide amorphous material into an aluminum oxide polycrystalline material after laterally recessing the sacrificial fill material layer; and

removing remaining portions of the sacrificial fill material layer after formation of the set of metal oxide blocking dielectric material portions.

24. The method of claim 20, wherein:

the monolithic three-dimensional memory device comprises a vertical NAND device located over the substrate;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;

the substrate comprises a silicon substrate;

the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.