SELECTIVE BLOCKING DIELECTRIC FORMATION IN A THREE-DIMENSIONAL MEMORY STRUCTURE

• US 20160172370A1
• Filed: 12/16/2014
• Published: 06/16/2016
• Est. Priority Date: 12/16/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: LIANG, Xiaofeng, MAKALA, Raghuveer S., SHARANGPANI, Rahul, KANAKAMEDALA, Senaka Krishna, MATAMIS, George, KOKA, Sateesh, ALSMEIER, Johann
• Granted Patent: US 9,484,357 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A plurality of blocking dielectric portions can be formed between a memory stack structure and an alternating stack of first material layers and second material layers by selective deposition of a dielectric material layer. The plurality of blocking dielectric portions can be formed after removal of the second material layers selective to the first material layers by depositing a dielectric material on surfaces of the memory stack structure while avoiding deposition on surfaces of the first material layers. A deposition inhibitor material layer or a deposition promoter material layer can be optionally employed. Alternatively, the plurality of blocking dielectric portions can be formed on surfaces of the second material layers while avoiding deposition on surfaces of the first material layers after formation of the memory opening and prior to formation of the memory stack structure. The plurality of blocking dielectric portions are vertically spaced annular structures.

Claims

1. A monolithic three-dimensional NAND memory device, comprising:

a stack of alternating layers comprising insulator layers and electrically conductive layers and located over a substrate;

a memory opening extending through the stack;

a lateral stack located within the memory opening and comprising, from outside to inside, a memory film and a semiconductor channel; and

a plurality of blocking dielectric portions vertically spaced from each other, comprising a dielectric metal oxide having a dielectric constant greater than 7.9, and contacting a respective portion of an outer sidewall of the memory film and a sidewall of a respective electrically conductive layer.

2. The monolithic three-dimensional NAND memory device of claim 1, wherein each of the plurality of blocking dielectric portions contacts at least one horizontal surface of the insulator layers.

3. The monolithic three-dimensional NAND memory device of claim 1, wherein the plurality of blocking dielectric portions comprise a material that is different from a material of the insulator layers.

4. The monolithic three-dimensional NAND memory device of claim 1, wherein:

the memory film comprises a memory material layer and a tunneling dielectric layer;

the plurality of blocking dielectric portions contacts an outer sidewall of the memory material layer; and

the plurality of blocking dielectric portions comprises a material that is different from a material of the memory material layer.

5. The monolithic three-dimensional NAND memory device of claim 4, wherein a material of the memory material layer has a hydrophobicity that is different from a hydrophobicity of a material of the insulator layers.

6. The monolithic three-dimensional NAND memory device of claim 1, further comprising a plurality of dielectric material portions that are vertically spaced apart, comprising a different material than the plurality of blocking dielectric portions, and contacting an overlying blocking dielectric portion and an underlying blocking dielectric portion.

7. The monolithic three-dimensional NAND memory device of claim 6, wherein each of the plurality of dielectric material portions contact a sidewall of a respective insulator layer.

8. The monolithic three-dimensional NAND memory device of claim 6, wherein a dielectric material portion among the plurality of dielectric material portions has a lesser vertical extent than one of the insulator layers that contacts the dielectric material portion.

9. The monolithic three-dimensional NAND memory device of claim 6, wherein a blocking dielectric portion among the plurality of blocking dielectric portions has a greater vertical extent than one of the electrically conductive layers that contacts the blocking dielectric portion.

10. The monolithic three-dimensional NAND memory device of claim 6, wherein the plurality of dielectric material portions and the plurality of blocking dielectric portions constitute an alternating stack of annular structures.

11. The monolithic three-dimensional NAND memory device of claim 1, wherein an outer sidewall of one of the plurality of blocking dielectric portions contacts an sidewall of one of the insulator layers.

12. The monolithic three-dimensional NAND memory device of claim 1, wherein the memory film comprises, from outside to inside, a blocking dielectric layer, a memory material layer, and a tunneling dielectric layer.

13. The monolithic three-dimensional NAND memory device of claim 12, wherein the plurality of blocking dielectric portions comprise a material that is different from a material of the blocking dielectric layer.

14. The monolithic three-dimensional NAND memory device of claim 12, wherein a material of the blocking dielectric layer has a hydrophobicity that is different from a hydrophobicity of a material of the insulator layers.

15. The monolithic three-dimensional NAND memory device of claim 12, wherein the blocking dielectric layer comprises silicon nitride, and the insulator layers comprise silicon oxide.

16. The monolithic three-dimensional NAND memory device of claim 15, further comprising an inner blocking dielectric layer contacting the blocking dielectric layer and the memory material layer.

17. The monolithic three-dimensional NAND memory device of claim 12, wherein the blocking dielectric layer is a contiguous layer that extends through an entirety of the stack of alternating layers, and each of the plurality of blocking dielectric portions contacts a portion of an outer sidewall of the blocking dielectric layer.

18. The monolithic three-dimensional NAND memory device of claim 17, wherein outer sidewalls of the plurality of blocking dielectric portions are laterally spaced farther away from the memory material layer than an outer sidewall of the blocking dielectric layer.

19. The monolithic three-dimensional NAND memory device of claim 17, wherein outer sidewalls of the plurality of blocking dielectric portions are laterally spaced by a same distance from the memory material layer as an outer sidewall of the blocking dielectric layer.

20. The monolithic three-dimensional NAND memory device of claim 19, wherein the blocking dielectric layer and the memory material layer have undulating inner sidewalls having a variable lateral distance from a vertical sidewall of the memory opening as a function of a height from a top surface of the substrate.

21. The monolithic three-dimensional NAND memory device of claim 1, wherein each of the plurality of blocking dielectric portions comprises a vertical portion, an upper laterally-protruding portion that protrudes outward from an outer sidewall of the vertical portion, and a lower laterally-protruding portion that protrudes outward from the outer sidewall of the vertical portion.

22. The monolithic three-dimensional NAND memory device of claim 1, wherein the plurality of blocking dielectric portions comprises aluminum oxide and the insulator layers comprise silicon oxide.

23. The monolithic three-dimensional NAND memory device of claim 1, wherein the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND memory device.

24. The monolithic three-dimensional NAND memory device of claim 14, wherein:

the substrate comprises a silicon substrate;

the NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in the first device level of the three-dimensional array of NAND strings is located over another memory cell in the second device level of the three-dimensional array of NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

each NAND string comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

25. A method of manufacturing a three-dimensional memory structure, comprising:

forming a stack of alternating layers comprising first material layers and second material layers over a substrate;

forming a memory opening through the stack;

forming a memory film and a semiconductor channel in the memory opening;

forming backside recesses by removing the second material layers selective to the first material layers; and

forming electrically conductive layers within the backside recesses,

wherein a plurality of blocking dielectric portions comprising a dielectric metal oxide is formed by a selective deposition process between the memory film and the respective electrically conductive layers.

26. The method of claim 25, wherein the plurality of blocking dielectric portions is formed in the backside recesses after formation of the backside recesses and prior to formation of the electrically conductive layers.

27. The method of claim 26, wherein:

the plurality of blocking dielectric portions is formed on physically exposed surface portions of the memory film in the backside recesses;

the physically exposed surface portions of the memory film has a hydrophobicity that is different from a hydrophobicity of the surfaces of the first material layers; and

the selective deposition process has a shorter incubation time on the physically exposed surface portions of the memory film than on the first material layer surfaces.

28. The method of claim 26, wherein:

the memory film comprises a lateral stack containing a blocking dielectric layer, a memory material layer and a tunneling dielectric layer; and

the plurality of blocking dielectric portions are formed on physically exposed surface portions of the silicon nitride layer.

29. The method of claim 28, further comprising etching physically exposed portions of the blocking dielectric layer in the backside recesses after removal of the second material layers to physically expose surface portions of the memory material layer in the backside recesses.

30. The method of claim 29, wherein the selective deposition process comprises selectively depositing the plurality of blocking dielectric portions on the physically exposed surface portions of the memory material layer in the backside recesses.

31. The method of claim 28, wherein remaining portions of the blocking dielectric layer comprises a plurality of dielectric material portions that are vertically spaced apart, comprising a different material than the plurality of blocking dielectric portions, and contacting an overlying blocking dielectric portion and an underlying blocking dielectric portion.

32. The method of claim 26, wherein:

the memory film comprises a lateral stack containing a blocking dielectric oxide-nitride-oxide film, a memory material layer and a tunneling dielectric;

the method comprises etching physically exposed oxide portions of the blocking dielectric layer in the back side recesses after removal of the second material layers to physically expose nitride surface portions of the blocking dielectric film; and

the selective deposition process comprises selectively depositing the plurality of blocking dielectric portions on the physically exposed nitride surface portions of the blocking dielectric film.

33. The method of claim 26, further comprising forming a deposition inhibitor material layer selectively on surfaces of the first material layers while the deposition inhibitor material layer is not formed on the physically exposed surface portions of the memory film, wherein the deposition inhibitor material layer comprises a material that suppresses deposition of the dielectric material of the plurality of blocking dielectric portions.

34. The method of claim 26, further comprising forming a deposition promoter material layer selectively on surfaces of the physically exposed surface portions of the memory film while the inhibitor material layer is not formed on the first material layers, wherein the deposition promoter material layer comprises a material that promotes deposition of the dielectric material of the plurality of blocking dielectric portions.

35. The method of claim 26, wherein each of the plurality of blocking dielectric portions comprises a vertical portion, an upper laterally-protruding portion that protrudes outward from an outer sidewall of the vertical portion, and a lower laterally-protruding portion that protrudes outward from the outer sidewall of the vertical portion.

36. The method of claim 25, wherein the plurality of blocking dielectric portions is formed on physically exposed surface portions of the second material layers in the memory opening after formation of the memory opening and prior to formation of the memory film.

37. The method of claim 36, further comprising:

forming backside recesses by removing the second material layers selective to the first material layers and to the plurality of blocking dielectric portions; and

forming electrically conductive layers on the plurality of blocking dielectric portions and the first material layers.

38. The method of claim 36, wherein:

surfaces of the second material layers in the memory opening has a different hydrophobicity from surfaces of the first material layers in the memory opening; and

the selective deposition process has a shorter incubation time on the surfaces of the second material layers than on the surfaces of the first material layers.

39. The method of claim 36, wherein the memory film comprises a blocking dielectric layer formed directly on the plurality of blocking dielectric portions exposed in the memory opening, a memory material layer formed on the blocking dielectric layer, and a tunneling dielectric layer formed on the memory material layer.

40. The method of claim 36, wherein each of the plurality of blocking dielectric portions is vertically spaced apart, and does not contact any other of the plurality of blocking dielectric portions.

41. The method of claim 36, further comprising laterally recessing sidewalls of the second material layers with respect to sidewalls of the first material layers, wherein the plurality of blocking dielectric portions is formed on the laterally recessed sidewalls of the second material layers.

42. The method of claim 36, wherein the memory material layer is formed with an undulating sidewall having a variable lateral distance from a vertical sidewall of the memory opening as a function of a height from a top surface of the substrate.

43. The method of claim 36, further comprising forming a blocking dielectric layer on the plurality of blocking dielectric portions, wherein the blocking dielectric layer is formed with an undulating sidewall having a variable lateral distance from a vertical sidewall of the memory opening as a function of a height from a top surface of the substrate.

44. The method of claim 25, wherein the memory structure comprises a vertical NAND device located over the substrate, wherein the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device.

45. The method of claim 44, wherein:

the substrate comprises a silicon substrate;

the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in the first device level of the three-dimensional array of NAND strings is located over another memory cell in the second device level of the three-dimensional array of NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

each NAND string comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.