HIGH- VOLTAGE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20160172490A1
• Filed: 12/16/2014
• Published: 06/16/2016
• Est. Priority Date: 12/16/2014
• Status: Active Grant

• Current Assignee: Vanguard International Semiconductor Corporation
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: LAO, Chung-Ren, LIU, Hsing-Chao, CHEN, Chu-Feng, CHOU, Wei-Chun
• Granted Patent: US 10,629,726 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first conductive type; a gate structure disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. The present disclosure also provides a method for manufacturing the high-voltage semiconductor device.

Claims

1. A high-voltage semiconductor device, comprising:

a substrate;

an epitaxial layer disposed over the substrate and having a first conductive a gate structure disposed over the epitaxial layer;

a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and

a stack structure disposed between the gate structure and the drain region, wherein the stack structure comprises;

a blocking layer;

an insulating layer disposed over the blocking layer; and

a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure.

2. The high-voltage semiconductor device as claimed in claim 1, further comprising:

a high-voltage well region disposed in the epitaxial layer and having a second conductive type, wherein the first conductive type is different from the second conductive type; and

a first conductive type doping region disposed in the high-voltage well region, wherein the source region is disposed in the first conductive type doping region, and the drain region is disposed in the high-voltage well region.

3. The high-voltage semiconductor device as claimed in claim 1, further comprising an insulating bump disposed between the gate structure and the drain region, wherein the stack structure conformally covers a portion of the insulating bump.

4. The high-voltage semiconductor device as claimed in claim 1, further comprising a plurality of insulating bumps disposed between the gate structure and the drain region, wherein the insulating bump which is closer to the drain region has a greater height.

5. The high-voltage semiconductor device as claimed in claim 3, wherein a material of the insulating bump comprises oxide, nitride, oxynitride or a combination thereof.

6. The high-voltage semiconductor device as claimed in claim 1, wherein the stack structure conformally covers a portion of the gate structure.

7. The high-voltage semiconductor device as claimed in claim 1, wherein the conductive layer electrically connects the gate structure through a first interconnection structure, and the conductive layer is electrically isolated from the source region.

8. The high-voltage semiconductor device as claimed in claim 1, Wherein the conductive layer electrically connects the source region through a first interconnection structure, and the conductive layer is electrically isolated from the gate structure.

9. The high-voltage semiconductor device as claimed in claim 1, wherein a material of the blocking layer comprises oxide, nitride, oxynitride or a combination thereof.

10. The high-voltage semiconductor device as claimed in claim 1, wherein a material of the insulating layer comprises oxide, nitride, oxynitride, low-k material or a combination thereof.

11. The high-voltage semiconductor device as claimed in claim 1, wherein a material of the conductive layer comprises metal, metal oxide, metal nitride, metal alloy, metal silicide or a combination thereof.

12. A method for manufacturing a high-voltage semiconductor device, comprises:

providing a substrate;

forming an epitaxial layer over the substrate, wherein the epitaxial layer has a first conductive type;

forming a gate structure over the epitaxial layer;

forming a source region and a drain region, wherein the source region and the drain region are disposed in the epitaxial layer at opposite sides of the gate structure respectively; and

forming a stack structure between the gate structure and the drain region, wherein the stack structure comprises;

a blocking layer;

an insulating layer disposed over the blocking layer; and

a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure.

13. The high-voltage semiconductor device as claimed in claim 12, further comprising:

before forming the gate structure, forming a high-voltage well region in the epitaxial layer, wherein the high-voltage well region has a second conductive type, and the first conductive type is different from the second conductive type; and

before forming the source region, forming a first conductive type doping region in the high-voltage well region, wherein the source region is disposed in the first conductive type doping region, and the drain region is disposed in the high-voltage well region.

14. The high-voltage semiconductor device as claimed in claim 12, further comprising:

before forming the gate structure, forming an insulating bump between the gate structure and the drain region, wherein the stack structure formed after the gate structure conformally covers a portion of the insulating bump.

15. The high-voltage semiconductor device as claimed in claim 12, further comprising:

before forming the gate structure, forming a plurality of insulating bumps between the gate structure and the drain region, wherein the insulating bump which is closer to the drain region has a greater height.

16. The high-voltage semiconductor device as claimed in claim 14, wherein a material of the insulating bump comprises oxide, nitride, oxynitride or is combination thereof.

17. The high-voltage semiconductor device as claimed in claim 12, wherein the stack structure conformally covers a portion of the gate structure.

18. The high-voltage semiconductor device as claimed in claim 12, wherein the conductive layer electrically connects the gate structure through a first interconnection structure, and the conductive layer is electrically isolated from the source region.

19. The high-voltage semiconductor device as claimed in claim 12, wherein the conductive layer electrically connects the source region through a first interconnection structure, and the conductive layer is electrically isolated from the gate structure.

20. The high-voltage semiconductor device as claimed in claim 12, wherein a material of the blocking layer comprises, oxide, nitride, oxynitride or a combination thereof.

21. The high-voltage semiconductor device as claimed in claim 12, wherein a material of the insulating layer comprises oxide, nitride, oxynitride, low-k material or a combination thereof.

22. The high-voltage semiconductor device as claimed in claim 12, wherein a material of the conductive layer comprises metal, metal oxide, metal nitride, metal alloy, metal silicide or as combination thereof.