METHOD FOR SEPARATING EPITAXIAL LAYERS FROM GROWTH SUBSTRATES, AND SEMICONDUCTOR DEVICE USING SAME

• US 20160172539A1
• Filed: 02/10/2016
• Published: 06/16/2016
• Est. Priority Date: 03/19/2012
• Status: Active Grant

• Current Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.)
• Inventors: HEO, Jeong Hun, Choi, Joo Won, Lee, Choong Min, Shin, Su Jin, Nam, Ki Bum, HAN, Yu Dae, LEE, A Ram Cha
• Granted Patent: US 9,882,085 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/025 Physical imperfections, e.g. particular concentration or distribution of impurities
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction

Abstract

The present invention relates to a method for separating epitaxial layers and growth substrates, and to a semiconductor device using same. According to the present invention, a semiconductor device is provided which comprises a supporting substrate and a plurality of semiconductor layers provided on the supporting substrate, wherein the uppermost layer of the semiconductor layers has a surface of non-uniform roughness.

Claims

1. A semiconductor device comprising:

a support substrate; and

a plurality of semiconductor layers formed on the support substrate,

wherein an uppermost layer of the semiconductor layers has a surface with non-uniform roughness.

2. The semiconductor device according to claim 1, wherein the surface of the uppermost layer comprises a cut surface of the uppermost layer.

3. The semiconductor device according to claim 1, wherein the surface of the uppermost layer comprises an exposed inner surface of a cut void.

4. The semiconductor device according to claim 1, wherein the surface of the uppermost layer comprises a plurality of V-shaped etched grooves formed by an etching liquid for etching the uppermost layer.

5. The semiconductor device according to claim 1, wherein the uppermost layer comprises an open region exposing another semiconductor layer under the uppermost layer.

6. The semiconductor device according to claim 1, wherein the semiconductor device comprises a light emitting diode, the semiconductor layers comprise at least an active layer, and the uppermost layer comprises an n-type semiconductor layer.

7. The semiconductor device according to claim 1, wherein the uppermost layer among the semiconductor layers comprises unmerged grooves on the surface thereof.

8. The semiconductor device according to claim 1, wherein the uppermost layer among the semiconductor layers comprises a convex-concave pattern and a rough surface.

9. The semiconductor device according to claim 8, wherein the rough surface comprises two surfaces having different roughness degrees.

10. The semiconductor device according to claim 8, wherein one of the two surfaces having different roughness degrees has the convex-concave pattern.

11. The semiconductor device according to claim 8, wherein one of the two surfaces having different roughness degrees comprises a surface formed by breaking a layer comprising cavities.

12-41. -41. (canceled)