DUAL LOOP VOLTAGE REGULATOR BASED ON INVERTER AMPLIFIER AND VOLTAGE REGULATING METHOD THEREOF

• US 20160173066A1
• Filed: 12/07/2015
• Published: 06/16/2016
• Est. Priority Date: 12/11/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Dae-Yong Kim
• Inventors: YANG, Junhyeok, KIM, Dae-Yong, YOO, Sungmin
• Granted Patent: US 9,577,613 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/01714 by bootstrapping, i.e. by positive feed-back
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

A voltage regulator includes a pass element, a buffer, and an error amplifier. The voltage regulator further includes a fast push-pull driver that has an inverter type amplification structure, is connected between a power output and a control input of the pass element, and reduces positive and negative peaks of the power output at a speed faster than a speed of a main feedback loop.

Claims

1. A voltage regulator comprising:

a pass element having a power input connected to a voltage source, a power output connected to a load, and a control input;

a buffer having an input and having an output connected to the control input of the pass element;

an error amplifier forming a first feedback loop together with the pass element and the buffer and having a positive input connected to a sampled voltage of the power output of the pass element, a negative input connected to a reference voltage, and an output connected to the input of the buffer; and

a fast push-pull driver connected between the power output and the control input of the pass element in an inverter type amplification structure and configured to reduce a negative peak and a positive peak of the power output due to a variation in the load at a speed faster than a voltage regulating speed of the first feedback loop.

2. The voltage regulator of claim 1, wherein the fast push-pull driver forms a second feedback loop together with the pass element, an operating speed of the second feedback loop being faster than an operating speed of the first feedback loop.

3. The voltage regulator of claim 1, wherein the fast push-pull driver comprises:

a first amplifier of an inverter type and configured to generate an inverting output in response to the power output of the pass element; and

a second amplifier of the inverter type and configured to generate a push driving current or a pull driving current for controlling a voltage level of the control input in response to the inverting output.

4. The voltage regulator of claim 3, wherein the fast push-pull driver further comprises a high-pass filter connected to the power output of the pass element and configured to perform alternating current (AC) coupling.

5. The voltage regulator of claim 4, wherein:

the first amplifier comprises a first PMOS transistor having a source connected to a power supply voltage, a gate connected to the power output, and a drain connected to the inverting output; and

a first NMOS transistor having a drain connected to the inverting output, a gate connected to the power output, and a source connected to a ground voltage, and

the second amplifier comprises a second PMOS transistor having a source connected to the power supply voltage, a gate connected to the inverting output, and a drain connected to the control input; and

a second NMOS transistor having a drain connected to the control input, a gate connected to the inverting output, and a source connected to the ground voltage.

6. The voltage regulator of claim 4, wherein:

the first amplifier comprises a first current source connected to a power supply voltage;

a first PMOS transistor having a source connected to an output of the first current source, a gate connected to the power output, and a drain connected to the inverting output;

a first NMOS transistor having a drain connected to the inverting output and a gate connected to the power output; and

a second current source connected between a source of the first NMOS transistor and a ground voltage, and

the second amplifier comprises a third current source connected to the power supply voltage;

a second PMOS transistor having a source connected to an output of the second current source, a gate connected to the inverting output, and a drain connected to the control input;

a second NMOS transistor having a drain connected to the control input and a gate connected to the inverting output; and

a fourth current source connected between a source of the second NMOS transistor and the ground voltage.

7. The voltage regulator of claim 4, wherein:

the first amplifier comprises a first PMOS transistor having a source connected to a power supply voltage and a gate connected to the power output;

a third PMOS transistor having a source connected to a drain of the first PMOS transistor, a gate connected to the power output, and a drain connected to the inverting output;

a first NMOS transistor having a gate connected to the power output and a source connected to a ground voltage; and

a third NMOS transistor having a drain connected to the inverting output, a gate connected to the power output, and a source connected to a drain of the first NMOS transistor; and

the second amplifier comprises a second PMOS transistor having a source connected to the power supply voltage and a gate connected to the inverting output;

a fourth PMOS transistor having a source connected to a drain of the second PMOS transistor, a gate connected to the inverting output, and a drain connected to the control input;

a second NMOS transistor having a gate connected to the inverting output and a source connected to the ground voltage;

and a fourth NMOS transistor having a drain connected to the control input, a gate connected to the inverting output, and a source connected to a drain of the second NMOS transistor.

8. The voltage regulator of claim 4, wherein:

the first amplifier comprises a first PMOS transistor having a source connected to a power supply voltage and a gate connected to the power output;

a third PMOS transistor having a source connected to a drain of the first PMOS transistor, a gate connected to a first control voltage, and a drain connected to the inverting output;

a first NMOS transistor having a gate connected to the power output and a source connected to a ground voltage; and

a third NMOS transistor having a drain connected to the inverting output, a gate connected to a second control voltage, and a source connected to a drain of the first NMOS transistor; and

the second amplifier comprises a second PMOS transistor having a source connected to the power supply voltage and a gate connected to the inverting output;

a fourth PMOS transistor having a source connected to a drain of the second PMOS transistor, a gate connected to the first control voltage, and a drain connected to the control input;

a second NMOS transistor having a gate connected to the inverting output and a source connected to the ground voltage; and

a fourth NMOS transistor having a drain connected to the control input, a gate connected to the second control voltage, and a source connected to a drain of the second NMOS transistor.

9. The voltage regulator of claim 4, wherein:

the first amplifier comprises a first PMOS transistor having a source connected to a power supply voltage and a gate connected to the power output;

a third PMOS transistor having a source connected to a drain of the first PMOS transistor and a gate connected to the power output;

a first NMOS transistor having a gate connected to the power output and a source connected to a ground voltage; and

a third NMOS transistor having a drain connected to a drain of the third PMOS transistor, a gate connected to the power output, and a source connected to a drain of the first NMOS transistor; and

the second amplifier comprises a second PMOS transistor having a source connected to the power supply voltage, a gate connected to the drain of the first PMOS transistor, and a drain connected to the control input; and

a second NMOS transistor having a gate connected to the drain of the first NMOS transistor, a drain connected to the control input, and a source connected to the ground voltage.

10. The voltage regulator of claim 1, further comprising a frequency compensation element connected between the power output of the pass element and the input of the buffer and configured to stabilize a frequency of a whole circuit loop.

11. A voltage regulator comprising:

a pass element having a power input connected to a voltage source, a power output connected to a load, and a control input;

a buffer having an input and having an output connected to the control input of the pass element;

an error amplifier forming a first feedback loop together with the pass element and the buffer and having a positive input connected to a divided voltage of the power output of the pass element, a negative input connected to a reference voltage, and an output connected to an input of the buffer; and

a fast push-pull driver connected between the power output and the control input of the pass element in an inverter type amplification structure and configured to regulate the power output at a speed faster than a regulating speed of the first feedback loop while alternating current (AC) coupling the power output when an undershoot and an overshoot of the power output occur due to a variation in the load.

12. The voltage regulator of claim 11, wherein the pass element comprises a PMOS transistor having a source connected to the power input, a drain connected to the power output, and a gate connected to the control input.

13. The voltage regulator of claim 12, wherein the buffer has a source follower circuit structure to relieve a slew limitation according to a variation in the power output and to respond at a high speed at a wide band.

14. The voltage regulator of claim 13, wherein the error amplifier comprises a differential amplifier configured to compare voltages of the positive and negative inputs and amplify a difference between the voltages of the positive and negative inputs.

15. The voltage regulator of claim 11, wherein:

the fast push-pull driver forms a second feedback loop together with the pass element, an operating response of the second feedback loop being faster than that of the first feedback loop, and

the first feedback loop functions as a direct current (DC) feedback loop and the second feedback loop functions as an AC feedback loop.

16. A low drop-out voltage regulator comprising:

a pass element configured to pass a power input to a power output connected to a load in response to a voltage on a control input;

a voltage divider configured to divide the power output according to a designated resistance ratio to generate a division output;

a buffer having an input and having an output connected to the control input of the pass element;

an error amplifier forming a first feedback loop together with the pass element and the buffer and configured to compare and amplify a voltage of a positive input connected to the division output of the voltage divider and a voltage of a negative input connected to an input reference voltage, an output of the error amplifier being provided as an input of the buffer; and

a fast push-pull driver having an inverter type amplification structure and configured to regulate the power output to a target voltage at a speed faster than a voltage regulating speed of the first feedback loop, when a negative peak or a positive peak deviating from the target voltage of the power output occurs due to a variation in the load.

17. The low drop-out voltage regulator of claim 16, wherein the low drop-out voltage regulator is installed in a package of a system on chip.

18. The low drop-out voltage regulator of claim 16, wherein the voltage divider comprises:

a first resistor having one end connected to the power output; and

a second resistor connected between the other end of the first resistor, from which the division voltage is generated, and a ground voltage.

19. The low drop-out voltage regulator of claim 16, wherein the fast push-pull driver has cascaded amplifiers of an inverter type and driving push and pull currents, the number of stages of the cascaded amplifiers being at least two or more.

20. The low drop-out voltage regulator of claim 19, wherein the fast push-pull driver further comprises a high-pass filter configured to alternating current (AC) couple the power output of the pass element using a capacitor and a resistor.

21-54. -54. (canceled)