ELECTRICAL CIRCUIT ODOMETER SENSOR ARRAY

• US 20160178694A1
• Filed: 12/18/2014
• Published: 06/23/2016
• Est. Priority Date: 12/18/2014
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Fry, Jonathan R., Klabes, Christopher, Schlichting, Kathryn E., Martin, Andrew J., McGahay, Vincent J., Smith, Melissa A.
• Granted Patent: US 10,060,974 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01C 22/00 Measuring distance traversed on the ground by vehicles, persons, animals or other moving solid bodies, e.g. using odometers, using pedometers
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2896 Testing of IC packages; Test features related to IC packages containers per se H01L23/02, encapsulations per se H01L23/28

Abstract

Approaches for detecting wear in integrated circuit chips are provided. An on-chip sensor system includes an integrated circuit chip including a plurality of sensor groups. Each respective one of the sensor groups is structured and arranged to detect a measure of wear corresponding to a respective one of a plurality of failure mechanisms.

Claims

1. An on-chip sensor system, comprising:

an integrated circuit chip comprising a plurality of sensor groups, wherein each respective one of the sensor groups is structured and arranged to detect a measure of wear corresponding to a respective one of a plurality of failure mechanisms.

2. The system of claim 1, wherein the plurality of sensor groups are arranged in an array, where plural instances of the array are at different locations on the chip.

3. The system of claim 1, wherein the plurality of failure mechanisms comprise at least one of:

stress induced voids at a material-to-material interface;

stress induced shorting due to metal migration;

dielectric material breakdown; and

transistor failure.

4. The system of claim 1, further comprising a monitoring core on the chip and operatively connected to each one of the plurality of sensor groups.

5. The system of claim 4, wherein the monitoring core is configured to dynamically adjust operation of the chip based on a detected state of at least one of the plurality of sensor groups.

6. The system of claim 4, wherein the monitoring core is configured to send a communication to an off-chip device based on a detected state of at least one of the plurality of sensor groups.

7. The system of claim 1, wherein the plurality of sensor groups comprises:

a first sensor group comprising first sensor structures that are configured to indicate different amounts of wear based on a first one of the plurality of failure mechanisms; and

a second sensor group comprising second sensor structures that are configured to indicate different amounts of wear based on a second one of the plurality of failure mechanisms.

8. The system of claim 7, wherein each of the first sensor structures comprises a metal via extending vertically between an upper metal wire and a lower metal wire.

9. The system of claim 7, wherein:

a first one of the first sensor structures is structured and arranged to develop a void at an interface between a first via and a first wire based on a first level of exposure to the first one of the plurality of failure mechanisms;

a second one of the first sensor structures is structured and arranged to develop a void at an interface between a second via and a second wire based on a second level of exposure to the first one of the plurality of failure mechanisms;

a third one of the first sensor structures is structured and arranged to develop a void at an interface between a third via and a third wire based on a third level of exposure to the first one of the plurality of failure mechanisms; and

the first level of exposure, the second level of exposure, and the third level of exposure are all different from one another.

10. The system of claim 7, wherein each of the second sensor structures comprises a metal wire extending horizontally between two metal vias.

11. The system of claim 7, wherein:

a first pair of the second sensor structures is structured and arranged to develop an electrical short based on a first level of exposure to the second one of the plurality of failure mechanisms;

a second pair of the second sensor structures is structured and arranged to develop an electrical short based on a second level of exposure to the second one of the plurality of failure mechanisms;

a third pair of the second sensor structures is structured and arranged to develop an electrical short based on a third level of exposure to the second one of the plurality of failure mechanisms; and

the first level of exposure, the second level of exposure, and the third level of exposure are all different from one another.

12. The system of claim 7, wherein:

there is a first spacing between a first one of the second sensor structures and a second one of the second sensor structures;

there is a second spacing between the second one of the second sensor structures and a third one of the second sensor structures;

there is a third spacing between the third one of the second sensor structures and a fourth one of the second sensor structures;

the second spacing is greater than the first spacing; and

the third spacing is greater than the second spacing.

13. The system of claim 7, wherein:

the plurality of sensor groups comprises a third sensor group comprising third sensor structures that are configured to indicate different amounts of wear based on a third one of the plurality of failure mechanisms;

the first one of the plurality of failure mechanisms comprises stress induced voids at a material-to-material interface;

the second one of the plurality of failure mechanisms comprises stress induced shorting due to metal migration; and

the third one of the plurality of failure mechanisms comprises dielectric material breakdown.

14. The system of claim 1, wherein:

the chip additionally comprises an operational transistor that is separate from the plurality of sensor groups; and

one of the plurality of sensor groups comprises a stressed transistor that is operated at least one of a higher voltage, a higher temperature, and a higher frequency than the operational transistor.

15. A semiconductor device, comprising:

a plurality of graduated sensor structures that are configured to fail sequentially at different levels of exposure to a particular failure mechanism,

wherein the sensor structures are formed in a die portion of an integrated circuit chip.

16. The device of claim 15, wherein:

the plurality of graduated sensor structures comprise first sensor structures;

the particular failure mechanism is a first failure mechanism; and

the chip further comprises a plurality of second sensor structures that are configured to fail sequentially at different levels of exposure to a second failure mechanism that is different than the first failure mechanism; and

the chip comprises plural instances of the first sensor structures and the second sensor structures at different locations on the chip.

17. The device of claim 16, further comprising a monitoring core on the chip, wherein the monitoring core is configured to perform at least one of:

dynamically adjust operation of the chip based on a detected state of at least one of the first sensor structures and the second sensor structures; and

send a communication to an off-chip device based on the detected state of at least one of the first sensor structures and the second sensor structures.

18. A method of determining an amount of wear on a semiconductor device, comprising:

detecting failure of a particular sensor structure comprised in a group of graduated sensor structures that are structured and arranged to fail sequentially due to exposure to a first failure mechanism, wherein the sensor structures are formed in the semiconductor device; and

correlating the failure of the particular sensor structure to an amount of wear experienced by the semiconductor device.

19. The method of claim 18, further comprising adjusting performance of a component of the semiconductor device based on the detecting, wherein the detecting and the adjusting are performed by a monitor core incorporated in the semiconductor device.

20. The method of claim 18, further comprising sending a message to a device that is external to the semiconductor device, wherein the detecting and the sending are performed by a monitor core incorporated in the semiconductor device, and the sending is based on the detecting.