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INSTRUCTION AND LOGIC FOR SHIFT-SUM MULTIPLIER

  • US 20160179514A1
  • Filed: 12/22/2014
  • Published: 06/23/2016
  • Est. Priority Date: 12/22/2014
  • Status: Active Grant
First Claim
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1. A processor, comprising:

  • a front end including a decoder, the decoder including a first logic to identify a multiplication instruction to multiply a first number and a second number;

    an execution unit including;

    a second logic to execute the multiplication instruction;

    a third logic to, based on the instruction, access a look-up table based on the second number to determine a plurality of shift parameters and one or more flag parameters; and

    a shift-sum-multiplier (SSM) including;

    a fourth logic to use the shift parameters to shift the first number to determine a plurality of partial products, and the flag parameters to determine signs of the partial products; and

    a fifth logic to sum the partial products to yield a result of the multiplication instruction; and

    a retirement unit including a sixth logic to retire the instruction.

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