INSTRUCTION AND LOGIC FOR SHIFT-SUM MULTIPLIER

• US 20160179514A1
• Filed: 12/22/2014
• Published: 06/23/2016
• Est. Priority Date: 12/22/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Oron, Shaul, Michael, Gilad
• Granted Patent: US 9,678,749 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 7/527 in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel G06F7/533 takes precedence
• CPC Class Codes: G06F 7/5306 with row wise addition of partial products G06F7/5324 takes precedence
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
• CPC Class Codes: G06F 9/4552 Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM

Abstract

A processor includes a front end including a decoder, an execution unit including a shift-sum multiplier (SSM), and a retirement unit. The decoder includes logic identify a multiplication instruction to multiply a first number and a second number. The execution unit includes logic to, based on the instruction, access a look-up table based on the second number to determine a plurality of shift parameters and one or more flag parameters. The SSM includes logic to use the shift parameters to shift the first number to determine a plurality of partial products, and the flag parameters to determine signs of the partial products. The SSM also includes logic to sum the partial products to yield a result of the multiplication instruction.

Claims

1. A processor, comprising:

a front end including a decoder, the decoder including a first logic to identify a multiplication instruction to multiply a first number and a second number;

an execution unit including;

a second logic to execute the multiplication instruction;

a third logic to, based on the instruction, access a look-up table based on the second number to determine a plurality of shift parameters and one or more flag parameters; and

a shift-sum-multiplier (SSM) including;

a fourth logic to use the shift parameters to shift the first number to determine a plurality of partial products, and the flag parameters to determine signs of the partial products; and

a fifth logic to sum the partial products to yield a result of the multiplication instruction; and

a retirement unit including a sixth logic to retire the instruction.

2. The processor of claim 1, wherein:

the shift parameters and flag parameters include a first shift parameter, a second shift parameter, and a first flag parameter; and

the SSM further includes;

a sixth logic to bitwise shift the first number to the right a number of times equal to the first shift parameter to generate a first partial product;

a seventh logic to bitwise shift the second number to the right a number of times equal to the second shift parameter to generate a second partial product; and

an eighth logic to set the second partial product as positive or negative based upon the first flag parameter.

3. The processor of claim 2, wherein the execution unit further includes a ninth logic to access the lookup table and retrieve the first shift parameter, second shift parameter, and first flag parameter based upon a value range of the second number, the value range from zero to one.

4. The processor of claim 1, wherein:

every shift parameter corresponds to an associated flag parameter; and

the SSM further includes;

a sixth logic to bitwise shift a given shift parameter to the right a number of times equal to the given shift parameter to generate a given partial product; and

a seventh logic to set the given partial product as positive or negative based upon the flag parameter associated with the given shift parameter.

5. The processor of claim 4, wherein the execution unit further includes an eighth logic to access the lookup table and retrieve the associated shift parameters and flag parameters based upon a value range of the second number, the value range from negative two to two.

6. The processor of claim 1, wherein the execution unit further includes a sixth logic to access the look-up table with a determined entry in the table that is closest in value to the second number.

7. The processor of claim 1, wherein the lookup table is to define, for a given value of the second number:

how many times the first number will be rotated to the right to generate an associated partial product of the multiplication instruction; and

a sign of the associated partial product.

8. A method comprising, within a processor:

identifying and decoding a multiplication instruction to multiply a first number and a second number;

based on the instruction, accessing a look-up table based on the second number to determine a plurality of shift parameters and one or more flag parameters; and

determining a plurality of partial products using the shift parameters to shift the first number and the flag parameters to determine signs of partial products; and

summing the partial products to yield a result of the multiplication instruction; and

retiring the instruction.

9. The method of claim 8, wherein:

the shift parameters and flag parameters include a first shift parameter, a second shift parameter, and a first flag parameter; and

the method further comprises;

bitwise shifting the first number to the right a number of times corresponding to the first shift parameter to generate a first partial product;

bitwise shifting the second number to the right a number of times corresponding to the second shift parameter to generate a second partial product; and

setting the second partial product as positive or negative based upon the first flag parameter.

10. The method of claim 9, further comprising accessing the lookup table and retrieve the first shift parameter, second shift parameter, and first flag parameter based upon a value range of the second number, the value range from zero to one.

11. The method of claim 8, wherein:

every shift parameter corresponds to a corresponding flag parameter; and

the method further comprises;

bitwise shifting a given shift parameter to the right a number of times corresponding to the given shift parameter to generate a given partial product; and

setting set the given partial product as positive or negative based upon the flag parameter corresponding to the given shift parameter.

13. The method of claim 8, further comprising accessing the look-up table by determining an entry in the table that is closest in value to the second number.

12. The method of claim 12, further comprising includes an eighth logic to access the lookup table and retrieve the corresponding shift parameters and flag parameters based upon a value range of the second number, the value range from negative two to two.

14. A system comprising:

a front end including a decoder, the decoder including a first logic to identify a multiplication instruction to multiply a first number and a second number;

an execution unit including;

a second logic to execute the multiplication instruction;

a third logic to, based on the instruction, access a look-up table based on the second number to determine a plurality of shift parameters and one or more flag parameters; and

a shift-sum-multiplier (SSM) including;

a fourth logic to use the shift parameters to shift the first number to determine a plurality of partial products, and the flag parameters to determine signs of the partial products; and

a fifth logic to sum the partial products to yield a result of the multiplication instruction; and

a retirement unit including a sixth logic to retire the instruction.

15. The system of claim 14, wherein:

the shift parameters and flag parameters include a first shift parameter, a second shift parameter, and a first flag parameter; and

the SSM further includes;

a sixth logic to bitwise shift the first number to the right a number of times equal to the first shift parameter to generate a first partial product;

a seventh logic to bitwise shift the second number to the right a number of times equal to the second shift parameter to generate a second partial product; and

an eighth logic to set the second partial product as positive or negative based upon the first flag parameter.

16. The system of claim 15, wherein the execution unit further includes a ninth logic to access the lookup table and retrieve the first shift parameter, second shift parameter, and first flag parameter based upon a value range of the second number, the value range from zero to one.

17. The system of claim 14, wherein:

every shift parameter corresponds to an associated flag parameter; and

the SSM further includes;

a sixth logic to bitwise shift a given shift parameter to the right a number of times equal to the given shift parameter to generate a given partial product; and

a seventh logic to set the given partial product as positive or negative based upon the flag parameter associated with the given shift parameter.

18. The system of claim 17, wherein the execution unit further includes an eighth logic to access the lookup table and retrieve the associated shift parameters and flag parameters based upon a value range of the second number, the value range from negative two to two.

19. The system of claim 14, wherein the execution unit further includes a sixth logic to access the look-up table by determined an entry in the table that is closest in value to the second number.

20. The system of claim 14, wherein the lookup table is to define, for a given value of the second number:

how many times the first number will be rotated to the right to generate an associated partial product of the multiplication instruction; and

a sign of the associated partial product.