NON-SERIALIZED PUSH INSTRUCTION FOR PUSHING A MESSAGE PAYLOAD FROM A SENDING THREAD TO A RECEIVING THREAD

• US 20160179517A1
• Filed: 12/23/2014
• Published: 06/23/2016
• Est. Priority Date: 12/23/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: STARKE, WILLIAM J., ARIMILLI, LAKSHMINARAYANA B., DRERUP, BERNARD C., GUTHRIE, GUY L., IRISH, JOHN D., STUECHELI, JEFFREY A.
• Granted Patent: US 9,766,890 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues

Abstract

In at least some embodiments, a processor core executes a sending thread including a first push instruction and a second push instruction subsequent to the first push instruction in a program order. Each of the first and second push instructions requests that a respective message payload be pushed to a mailbox of a receiving thread. In response to executing the first and second push instructions, the processor core transmits respective first and second co-processor requests to a switch in the data processing system via an interconnect fabric of the data processing system. The processor core transmits the second co-processor request to the switch without regard to acceptance of the first co-processor request by the switch.

Claims

1-7. -7. (canceled)

8. A processing unit for a data processing system including a switch, the processing unit comprising:

a memory; and

a processor core coupled to the memory, wherein the processor core includes at least one execution unit that executes, in a sending thread, a first push instruction and a second push instruction subsequent to the first push instruction in a program order, wherein each of the first and second push instructions requests that a respective message payload be pushed to a mailbox of a receiving thread;

wherein the processor core, in response to executing the first and second push instructions, transmits respective first and second co-processor requests to the switch in the data processing system via an interconnect fabric of the data processing system, wherein the processor core transmits the second co-processor request to the switch without regard to acceptance of the first co-processor request by the switch.

9. The processing unit of claim 8, wherein the processor core executes the first and second push instructions without regard to the program order.

10. The processing unit of claim 8, wherein the processor core transmits, in each of the first and second co-processor requests, a software-supplied sequence number that orders the respective message payloads of the first and second push instructions.

11. The processing unit of claim 8, wherein:

the data processing system includes multiple switches including the switch;

the first push instruction includes a co-processor type parameter that identifies the switch as responsible for servicing the first co-processor request; and

the processor core transmits, with the first co-processor request, the co-processor type parameter.

12. The processing unit of claim 8, wherein:

the switch includes a data structure including a plurality of entries;

the push instruction includes a logical window parameter that identifies a particular entry among the plurality of entries in the data structure in the switch that is to be used to transmit the message payload of the first push instruction; and

the processor core transmits, with the first co-processor request, the logical window parameter.

13. The processing unit of claim 8, wherein:

the push instruction includes a report enable parameter; and

the processor core, responsive to the report enable parameter having an enabled state, transmits, with the first co-processor request, the report enable parameter to request notification of the receiving thread of injection of the message payload of the first push instruction into the mailbox of the receiving thread.

14. The processing unit of claim 8, wherein:

the push instruction includes a completion enable parameter; and

the processor core, responsive to the completion enable parameter having an enabled state, transmits, with the first co-processor request, the completion enable parameter to request notification of the sending thread of injection of the message payload of the first push instruction into the mailbox of the receiving thread.

15. A data processing system, comprising:

a memory;

an interconnect fabric;

a processor core coupled to the memory and to the interconnect fabric, wherein the processor core includes at least one execution unit that executes, in a sending thread, a first push instruction and a second push instruction subsequent to the first push instruction in a program order, wherein each of the first and second push instructions requests that a respective message payload be pushed to a mailbox of a receiving thread, and wherein the processor core, in response to executing the first and second push instructions, transmits respective first and second co-processor requests to the switch in the data processing system via an interconnect fabric of the data processing system; and

a switch, coupled to the interconnect fabric, that responsive to acceptance of the first co-processor request, injects the respective message payload of the first co-processor request into the mailbox of the receiving thread, and that, responsive to acceptance of the second co-processor request, injects the respective message payload of the second co-processor request into the mailbox of the receiving thread, wherein the processor core transmits the second co-processor request to the switch without regard to acceptance of the first co-processor request by the switch.

16. The data processing system of claim 15, wherein the processor core executes the first and second push instructions without regard to the program order.

17. The data processing system of claim 15, wherein the processor core transmits, in each of the first and second co-processor requests, a software-supplied sequence number that orders the respective message payloads of the first and second push instructions.

18. The data processing system of claim 15, wherein:

the data processing system includes multiple switches including the switch;

the first push instruction includes a co-processor type parameter that identifies the switch as responsible for servicing the first co-processor request; and

the processor core transmits, with the first co-processor request, the co-processor type parameter.

19. The data processing system of claim 15, wherein:

the switch includes a data structure including a plurality of entries;

the push instruction includes a logical window parameter that identifies a particular entry among the plurality of entries in the data structure in the switch that is to be used to transmit the message payload of the first push instruction; and

the processor core transmits, with the first co-processor request, the logical window parameter.

20. The data processing system of claim 15, wherein:

the push instruction includes a report enable parameter; and

the processor core, responsive to the report enable parameter having an enabled state, transmits, with the first co-processor request, the report enable parameter to request notification of the receiving thread of injection of the message payload of the first push instruction into the mailbox of the receiving thread.