UPDATING PERSISTENT DATA IN PERSISTENT MEMORY-BASED STORAGE

• US 20160179687A1
• Filed: 12/22/2014
• Published: 06/23/2016
• Est. Priority Date: 12/22/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: KUMAR, SANJAY, SANKARAN, RAJESH, DULLOOR, SUBRAMANYA, LI, SHENG
• Granted Patent: US 9,430,396 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3476 Data logging G06F11/14, G06F11/2205 take precedence
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2201/87 Monitoring of transactions
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0671 In-line storage system

Abstract

A processor includes a processing core to execute an application including instructions encoding a transaction with a persistent memory via a volatile cache that includes a cache line associated with the transaction, the cache line being associated with a cache line status, and a cache controller operatively coupled to the volatile cache, the cache controller, in response to detecting a failure event, to, in response to determining that the cache line status that the cache line is committed, evict contents of the cache line to the persistent memory, and in response to determining that the cache line status indicating that the cache line is uncommitted, discard the contents of the cache line.

Claims

1. A processor comprising:

a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a volatile cache, wherein the volatile cache comprises a cache line associated with the transaction, the cache line being associated with a cache line status; and

a cache controller operatively coupled to the volatile cache, the cache controller, in response to detecting a failure event, to;

in response to determining that the cache line status indicates that the cache line is committed, evict contents of the cache line to the persistent memory, and

in response to determining the cache line status indicates that the cache line is uncommitted, discard the contents of the cache line.

2. The processor of claim 1, wherein the processing core is to execute a transaction begin instruction to initiate the transaction, and a transaction end instruction to conclude the transaction.

3. The processor of claim 2, wherein the processing core is to execute a system call to a kernel to acquire a transaction identifier prior to executing the transaction begin instruction and to store the transaction identifier in a transaction identifier register, and wherein the processing core is further to copy the transaction identifier to the cache line to associate the cache line with the transaction.

4. The processor of claim 3, wherein the cache controller comprises a hash table referencing a plurality of dirty cache lines for a plurality of transactions whose contents are different from data stored in a corresponding location of the persistent memory.

5. The processor of claim 4, wherein, in response to the failure event, the processing core is to execute an abort instruction, and wherein executing the abort instruction comprises transmitting an abort message comprising the transaction identifier to the cache controller.

6. The processor of claim 5, wherein, in response to receiving the abort message, the cache controller is to identify and invalidate the plurality of dirty cache lines for the plurality of transactions based on the hash table.

7. The processor of claim 2, wherein, in response to detecting the transaction begin instruction, the cache controller is to assign the cache line a free state.

8. The processor of claim 2, wherein, in response to detecting a write to the location in the persistent memory by a second transaction, the cache controller is to assign the cache line the uncommitted state.

9. The processor of claim 2, wherein, in response to detecting the transaction end instruction, the cache controller is to assign the cache line the committed state atomically.

10. The processor of claim 2, wherein, in response to detecting a cache eviction event, the cache controller is to identify a plurality of cache lines whose cache line status flags do not indicate the uncommitted state and evict contents of the plurality of cache lines to the persistent memory.

11. The processor of claim 1, wherein, in response to detecting an overflow of cache lines in the cache, the cache controller is to evict at least one cache line to the persistent memory.

12. The processor of claim 11, wherein the cache controller is further to select the cache line to be evicted according to a policy of resource usage.

13. The processor of claim 11, wherein the persistent memory comprises a data log comprising at least one of a redo log or an undo log.

14. The processor of claim 11, further comprising a memory controller, wherein, in response to detecting the transaction end instruction, the cache controller is to instruct the memory controller to commit the evicted at least one cache line in the persistent memory.

15. The processor of claim 1, wherein the volatile cache is part of a near memory of a two-level memory system, and the persistent memory is part of a far memory of the two-level memory system.

16. The processor of claim 1, wherein the volatile cache is a last level cache (LLC) associated with the processor, and the persistent memory is part of a far memory of a one-level memory system.

17. A system-on-a-chip (SoC) comprising:

a two-level memory comprising a first level comprising a volatile cache, and a second level comprising a persistent memory, and

a processor, operatively coupled to the two-level memory, comprising;

a processing core, in response to receiving a transaction begin instruction, to store a transaction identifier in a transaction identifier register prior to executing a transaction with the persistent memory and to copy the transaction identifier to a cache line of the volatile cache; and

a cache controller to evict the cache line tagged with the transaction identifier from the cache to the persistent memory in response to a cache eviction event based on a commit state of the cache line.

18. The SoC of claim 17, wherein the cache controller, in response to detecting a failure event, to:

in response to determining a value of the cache line status flag being one of committed or free, evict data stored in the cache line to the persistent memory, and

in response to determining that the value of a cache line status flag associated with the cache line is uncommitted, discard the cache line.

19. The SoC of claim 18, wherein the processing core is to execute a system call to a kernel of an operating system to acquire the transaction identifier prior to executing the transaction begin instruction.

20. The SoC of claim 18, wherein the cache controller comprises a hash table referencing a plurality of dirty cache lines whose contents are different from data stored in a correspondingly location of the persistent memory.

21. A method comprising:

executing, by a processing core, an application comprising instructions encoding a transaction with a persistent memory via a volatile cache, wherein the volatile cache comprises a cache line associated with the transaction, the cache line being associated with a cache line status;

detecting a failure event occurred associated with the transaction, wherein the failure event requires a reboot of a system that the processing core supports;

in response to determining that a status flag of the cache line indicates a committed state, evicting contents of the cache line to the persistent memory; and

in response to determining that the status flag of the cache line indicates an uncommitted state, discarding the contents of the cache line.

22. The method of claim 21, wherein the processing core is to execute a transaction begin instruction to initiate the transaction, and a transaction end instruction to conclude the transaction.

23. The method of claim 22, further comprising:

executing a system call to a kernel to acquire a transaction identifier prior to executing the transaction begin instruction;

storing the transaction identifier in a transaction identifier register of the processor; and

copying the transaction identifier to the cache line to associate the cache line with the transaction.