DEVICE TABLE IN SYSTEM MEMORY

• US 20160179720A1
• Filed: 03/11/2016
• Published: 06/23/2016
• Est. Priority Date: 03/14/2014
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Craddock, David F., Gregg, Thomas A., Lais, Eric N.
• Application Number:
  US15/067,895
• Publication Number:
  US 20160179720A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements

Abstract

Embodiments relate to an implementation of a device table in system memory to which a peripheral component interface (PCI) adapter is coupled via a host bridge. An aspect includes an access of the device table in the system memory by a switch coupled to the host bridge, management of a device table entry (DTE) cache in the host bridge for coherency for DTE configuration changes and maintenance of a usage count and an in-use count in the host bridge for each cached DTE.

Claims

1. A method for implementing a device table in system memory to which a peripheral component interface (PCI) adapter is coupled via a host bridge, the method comprising:

accessing the device table in the system memory by the host bridge;

managing a device table entry (DTE) cache in the host bridge for coherency for DTE configuration changes; and

maintaining a usage count and an in-use count in the host bridge for each cached DTE, wherein;

the maintaining of the usage count comprises including one or more usage counters in the host bridge for association with a given PCI function and a corresponding DTE to be incremented by the host bridge as direct memory access (DMA) read or write requests are processed,

the maintaining of the in-use count comprises including an in-use count in a DTE to be incremented and decremented when address translation (AT) fetches are issued and returned, respectively, the method further comprising;

updating a DTE in the device table in the system memory and flushing a corresponding DTE of the DTE cache in the host bridge for a PCI instruction and synchronizing the PCI instruction with the flushing of the DTE;

updating error state bits in the device table in the system memory and the DTE cache; and

load response handling comprising blocking by the host bridge of all load responses based on a DTE being in an error state, blocking by the processor of all load responses based on a DTE being in an error state and receiving an indication to check by the host bridge, checking by the host bridge of the error state in the DTE cache based on the DTE for a load response being cached and clearing an error state in the DTE