IMPLEMENTING DRAM ROW HAMMER AVOIDANCE

• US 20160180900A1
• Filed: 04/24/2015
• Published: 06/23/2016
• Est. Priority Date: 12/17/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kilmer, Charles A., Lingambudi, Anil B., Maule, Warren E., Vidyapoornachary, Diyanesh Babu C.
• Granted Patent: US 10,453,503 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence

Abstract

A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.

Claims

1. A method for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system comprising:

providing hammer detection logic identifying a hit count of repeated activations at a specific row in the DRAM;

providing monitor and control logic receiving an output of the hammer detection logic for comparing the identified hit count value with a programmable threshold value, capturing an address responsive to the compared values and providing a selected row hammer avoidance action for the captured address.

2. The method as recited in claim 1 wherein providing the selected row hammer avoidance action for the captured address includes providing one or more read cycles for the captured address to eliminate hammering effect.

3. The method as recited in claim 1 wherein providing the selected row hammer avoidance action for the captured address includes providing command stream control for the captured address to ensure that a row hammer limit is not reached.

4. The method as recited in claim 1 wherein providing the selected row hammer avoidance action for the captured address includes triggering scrub operations over an address range of the captured address based on the threshold count.

5. The method as recited in claim 1 wherein providing the selected row hammer avoidance action for the captured address includes holding mainline activates, and releasing mainline activates after selected row hammer avoidance action is provided.

6. The method as recited in claim 1 wherein providing said monitor and control logic includes providing a threshold register for storing the programmable threshold value.

7. The method as recited in claim 1 wherein providing said monitor and control logic includes providing an address capture register for storing the captured address.

8. The method as recited in claim 1 wherein providing said monitor and control logic includes providing a hold register for holding and releasing mainline read and write operations.

9. The method as recited in claim 1 wherein providing said monitor and control logic includes providing a read cycle generator for generating one or more dummy read cycles for the captured address to eliminate hammering effect.

10-20. -20. (canceled)