DYNAMICALLY COMPENSATING FOR DEGRADATION OF A NON-VOLATILE MEMORY DEVICE

• US 20160180958A1
• Filed: 12/22/2014
• Published: 06/23/2016
• Est. Priority Date: 12/22/2014
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: RAGHUNATHAN, SHYAM SUNDER, CHAO, IWEN, KALAVADE, PRANAV, PARAT, KRISHNA K., ZHU, FENG, GUO, XIN
• Granted Patent: US 9,418,000 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1084 Degraded mode, e.g. caused by single or multiple storage removals or disk failures
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.

Claims

1. An electronic device, comprising:

at least one processor; and

at least one storage device comprising a nonvolatile memory; and

a controller coupled to the memory and comprising logic to;

monitor at least one performance parameter of a nonvolatile memory;

determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory; and

in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory selected from the group consisting of increasing an erase voltage threshold for the nonvolatile memory, increasing a program voltage threshold for the nonvolatile memory, increasing an erase start voltage for the nonvolatile memory, increasing a program start voltage for the nonvolatile memory, modify a seeding voltage for the nonvolatile memory, modifying a true-erase voltage (TEV), modifying an erase pulse timing (TE), and modifying a select gate voltage.

2. The electronic device of claim 1, wherein the at least one performance parameter comprises at least one of:

a number of program/erase cycles executed on the nonvolatile memory;

a write time parameter for executing write operations on the nonvolatile memory;

or

a read failure parameter for read operations on the nonvolatile memory.

3. The electronic device of claim 2, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase an erase voltage threshold for the nonvolatile memory.

4. The electronic device of claim 2, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase a program voltage threshold for the nonvolatile memory.

5. The electronic device of claim 2, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase an erase start voltage for the nonvolatile memory.

6. The electronic device of claim 2, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase a program start voltage for the nonvolatile memory.

7. The electronic device of claim 2, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to modify at least one of:

a seeding voltage for the nonvolatile memory;

a true-erase voltage (TEV);

an erase pulse timing (TE);

a select gate voltage.

8. A storage device, comprising:

a nonvolatile memory; and

a controller coupled to the memory and comprising logic to;

monitor at least one performance parameter of a nonvolatile memory;

determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory; and

in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory selected from the group consisting of increasing an erase voltage threshold for the nonvolatile memory, increasing a program voltage threshold for the nonvolatile memory, increasing an erase start voltage for the nonvolatile memory, increasing a program start voltage for the nonvolatile memory, modify a seeding voltage for the nonvolatile memory, modifying a true-erase voltage (TEV), modifying an erase pulse timing (TE), and modifying a select gate voltage.

9. The storage device of claim 8, wherein the at least one performance parameter comprises at least one of:

a number of program/erase cycles executed on the nonvolatile memory;

a write time parameter for executing write operations on the nonvolatile memory;

or

a read failure parameter for read operations on the nonvolatile memory.

10. The storage device of claim 9, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase an erase voltage threshold for the nonvolatile memory.

11. The storage device of claim 9, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase a program voltage threshold for the nonvolatile memory.

12. The storage device of claim 9, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase an erase start voltage threshold for the nonvolatile memory.

13. The storage device of claim 9, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase a program start voltage threshold for the nonvolatile memory.

14. The storage device of claim 9, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to modify at least one of:

a seeding voltage for the nonvolatile memory device;

a true-erase voltage (TEV);

an erase pulse timing (TE);

a select gate voltage.

15. A controller comprising logic, at least partially including hardware logic, to:

monitor at least one performance parameter of a nonvolatile memory;

determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory; and

in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory selected from the group consisting of increasing an erase voltage threshold for the nonvolatile memory, increasing a program voltage threshold for the nonvolatile memory, increasing an erase start voltage for the nonvolatile memory, increasing a program start voltage for the nonvolatile memory, modify a seeding voltage for the nonvolatile memory, modifying a true-erase voltage (TEV), modifying an erase pulse timing (TE), and modifying a select gate voltage.

16. The controller of claim 15, wherein the at least one performance parameter comprises at least one of:

a number of program/erase cycles executed on the nonvolatile memory;

a write time parameter for executing write operations on the nonvolatile memory;

or

a read failure parameter for read operations on the nonvolatile memory.

17. The controller of claim 16, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase an erase voltage threshold for the nonvolatile memory.

18. The controller of claim 16, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase a program voltage threshold for the nonvolatile memory.

19. The controller of claim 16, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase an erase start voltage for the nonvolatile memory.

20. The controller of claim 16, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase a program start voltage for the nonvolatile memory.

21. The controller of claim 16, wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to modify at least one of:

a seeding voltage for the nonvolatile memory device;

a true-erase voltage (TEV);

an erase pulse timing (TE);

a select gate voltage.