METHOD FOR FORMING A SPLIT-GATE FLASH MEMORY CELL DEVICE WITH A LOW POWER LOGIC DEVICE
First Claim
1. An embedded flash memory device comprising:
- a gate stack including a control gate arranged over a floating gate;
an erase gate arranged adjacent to a first side of the gate stack;
a word line arranged adjacent to a second side of the gate stack that is opposite the first side, wherein the word line includes a word line ledge exhibiting a reduced height relative to a top surface of the word line and on an opposite side of the word line as the gate stack;
a polysilicon logic gate with a top surface approximately even with the word line ledge;
an interlayer dielectric (ILD) layer arranged over the gate stack, the erase gate, the polysilicon logic gate, and the word line; and
a contact extending through the ILD layer to one of the erase gate, the word line, and the polysilicon logic gate.
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Accused Products
Abstract
An embedded flash memory device is provided. A gate stack includes a control gate arranged over a floating gate. An erase gate is arranged adjacent to a first side of the gate stack. A word line is arranged adjacent to a second side of the gate stack that is opposite the first side. The word line includes a word line ledge exhibiting a reduced height relative to a top surface of the word line and on an opposite side of the word line as the gate stack. A polysilicon logic gate has a top surface approximately even with the word line ledge. An ILD layer is arranged over the gate stack, the erase gate, the polysilicon logic gate, and the word lines. A contact extends through the ILD layer. A method of manufacturing the embedded flash memory device is also provided.
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Citations
31 Claims
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1. An embedded flash memory device comprising:
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a gate stack including a control gate arranged over a floating gate; an erase gate arranged adjacent to a first side of the gate stack; a word line arranged adjacent to a second side of the gate stack that is opposite the first side, wherein the word line includes a word line ledge exhibiting a reduced height relative to a top surface of the word line and on an opposite side of the word line as the gate stack; a polysilicon logic gate with a top surface approximately even with the word line ledge; an interlayer dielectric (ILD) layer arranged over the gate stack, the erase gate, the polysilicon logic gate, and the word line; and a contact extending through the ILD layer to one of the erase gate, the word line, and the polysilicon logic gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 21, 22)
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10-20. -20. (canceled)
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23. An integrated circuit for an embedded flash memory device, the integrated circuit comprising:
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a pair of gate stacks laterally spaced over a semiconductor substrate, wherein each of the gate stacks comprises a floating gate and a control gate arranged over the floating gate; an erase gate arranged between opposing bottommost sidewalls of the gate stacks; a pair of word lines arranged on opposite outer sidewalls of the gate stacks, wherein the word lines include word line ledges exhibiting reduced heights relative to top surfaces of the word lines; and a polysilicon logic gate with a top surface approximately even with the word line ledges. - View Dependent Claims (24, 25, 26, 27, 28, 29)
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30. An integrated circuit comprising:
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a memory cell comprising a gate stack arranged laterally between an erase gate and a word line, wherein the gate stack comprises a control gate arranged over a floating gate and a hard mask arranged over the control gate, and wherein the word line includes a ledge that is below a top surface of the word line; a logic device laterally spaced from the memory cell and comprising a gate electrode, wherein a top surface of the gate electrode is even with the ledge, and wherein the gate electrode and the word line have a same crystalline structure; and an interlayer dielectric (ILD) layer covering the memory cell and the logic device. - View Dependent Claims (31)
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Specification