SEMICONDUCTOR DEVICE HAVING DUAL WORK FUNCTION GATE STRUCTURE, METHOD FOR FABRICATING THE SAME, MEMORY CELL HAVING THE SAME, AND ELECTRONIC DEVICE HAVING THE SAME

• US 20160181377A1
• Filed: 03/02/2016
• Published: 06/23/2016
• Est. Priority Date: 12/16/2014
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: OH, Tae-Kyung
• Granted Patent: US 9,577,052 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect

Abstract

A semiconductor device includes a body including a first junction region; a pillar positioned over the body, and including a vertical channel region and a second junction region over the vertical channel region; a gate trench exposing side surfaces of the pillar; a gate dielectric layer covering the gate trench; and a gate electrode embedded in the gate trench, with the gate dielectric layer interposed therebetween. The gate electrode includes a first work function liner overlapping with the vertical channel region, and including an aluminum-containing metal nitride; a second work function liner overlapping with the second junction region, and including a silicon-containing non-metal material; and an air gap positioned between the second work function liner and the second junction region.

Claims

1-20. -20. (canceled)

21. A method for fabricating a semiconductor device, comprising:

forming a pillar;

forming a gate dielectric layer over a lower side surface and over an upper side surface of the pillar;

forming a gate electrode including a first work function liner over the lower side surface of the pillar;

forming a second work function liner over the upper side surface of the pillar,

forming a gap between the second work function liner and the upper side surface of the pillar;

capping the gap to form an air gap; and

forming a junction region in the pillar to have a depth that overlaps with the air gap and the second work function liner,

wherein the air gap is provided between the junction region and the second work function liner.

22. The method according to claim 21, wherein the forming of the pillar comprises:

preparing a substrate;

etching the substrate to form a line type active region;

patterning the line type active region to form an island type active region;

etching the island type active region to form a preliminary pillar; and

etching the preliminary pillar to form the pillar.

23. The method according to claim 21, wherein the forming of the gate electrode comprises:

forming a preliminary first work function liner over the lower side surface and the upper side surface of the pillar;

forming the second work function liner over the preliminary first work function liner; and

recessing the preliminary first work function liner to form the first work function liner, wherein the first work function liner does not extend over the second work function liner.

24. The method according to claim 21, wherein the first work function liner includes titanium aluminum nitride.

25. The method according to claim 21, wherein the second work function liner includes an N-type impurity-doped polysilicon.

26. The method according to claim 21, wherein the forming of the gate electrode comprises:

forming a first work function liner layer over the gate dielectric layer;

etching the first work function liner layer to form a preliminary first work function liner which is positioned on the lower side surface of the pillar;

forming a first low resistivity electrode over the preliminary first work function liner and at a level lower than a top surface of the pillar;

forming a second work function liner layer at a level higher than the first low resistivity electrode and the preliminary first work function liner;

forming a second low resistivity layer over the second work function liner layer;

recessing the second low resistivity layer and the second work function liner layer to form a second low resistivity electrode and the second work function liner at a level lower than the top surface of the pillar; and

recessing the preliminary first work function liner to non-overlap with the first work function liner, and forming the first work function liner and the gap.

27. The method according to claim 26, wherein the second low resistivity electrode is formed of a material which is non-reactive with the second work function liner,

wherein the first low resistivity electrode is formed of a fluorine-free material,

wherein the first low resistivity electrode is formed of a material which is non-reactive with the second work function liner.

28. The method according to claim 26, wherein the first low resistivity electrode is formed of a material which is non-reactive with the second work function liner, and

wherein the second low resistivity electrode is formed of a material which is reactive with the second work function liner.

29. The method according to claim 26, further comprising:

forming an upper barrier which is positioned between the second work function liner and the second low resistivity electrode.

30. The method according to claim 26, further comprising:

forming a lower barrier which is positioned between the first work function liner and the first low resistivity electrode; and

forming an upper barrier which is positioned between the second work function liner and the second low resistivity electrode.

31. The method according to claim 21, wherein the forming of the pillar comprises:

preparing a substrate;

etching the substrate to form a line type active region;

patterning the line type active region to form an island type active region;

etching the island type active region to form a bit line trench and a preliminary pillar;

etching the preliminary pillar to form a gate trench which crosses the bit line trench and the pillar, wherein the pillar has first, second, and third side surfaces and the gate trench expose the first side surface; and

forming a first branch trench and a second branch trench which expose the second and third side surfaces of the pillar by extending the gate trench.

32. The method according to claim 31, wherein the gate electrode comprises a first branch part which is positioned in the first branch trench and a second branch part which is positioned in the second branch trench.

33. A method for fabricating a semiconductor device, comprising:

preparing a substrate which includes a first junction region;

etching the substrate to form a first pillar and a second pillar which are separated from each other in a gate trench;

forming, in a gate trench, a preliminary gate electrode including (i) preliminary first work function liners over lower side surfaces and upper side surfaces of the first and second pillars, and (ii) second work function liners over the upper side surfaces of the first and second pillars;

separating the preliminary gate electrode, and forming a first gate electrode which overlaps with the upper and lower side surfaces of the first pillar and a second gate electrode which overlaps with the upper and lower side of the second pillar;

recessing the preliminary first work function liners to non-overlap with the second work function liners, and forming gaps;

capping the gaps, and forming air gaps; and

forming second junction regions in the first and second pillars to have a depth that overlaps with the air gaps,

wherein each of the first and second pillars has first, second, and third side surfaces and the gate trench expose the first side surface of the first and second pillars.

34. The method according to claim 33, wherein, before forming of the preliminary gate electrode, the method further comprises:

forming a first branch trench and a second branch trench which expose the second and third side surfaces of the first and second pillars by extending the gate trench.

35. The method according to claim 33, wherein the preparing of the substrate which includes the first junction region comprises:

preparing the substrate;

etching the substrate, and forming a body and a preliminary first pillar and a preliminary second pillar which are separated from each other by a bit line trench over the body;

forming the first junction region in the body over a bottom surface of the bit line trench; and

forming a bit line which is electrically coupled with the first junction region, in the bit line trench.

36. The method according to claim 35, wherein the forming of the preliminary first pillar and the preliminary second pillar comprises:

forming a first isolation layer, which defines a line type active region, in the substrate;

cutting the first isolation layer and the line type active region to form an isolation trench and an island type active region;

filling a second isolation layer in the isolation trench; and

etching the island type active region, the first isolation layer, and the second isolation layer to form the bit line trench.

37. The method according to claim 33, wherein the first work function liner includes titanium aluminum nitride.

38. The method according to claim 33, wherein the second work function liner includes an N-type impurity-doped polysilicon.

39. The method according to claim 33, wherein each gate electrode further comprises (i) a first low resistivity electrode which is provided over the first work function liner and (ii) a second low resistivity electrode which is provided over the second work function liner.

40. The method according to claim 39, wherein each gate electrode further comprises an upper barrier between the second work function liner and the second low resistivity electrode.