PARTIAL SPACER FOR INCREASING SELF ALIGNED CONTACT PROCESS MARGINS

• US 20160181392A1
• Filed: 12/19/2014
• Published: 06/23/2016
• Est. Priority Date: 12/19/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Alptekin, Emre, Ramachandran, Ravikumar, Sardesai, Viraj Y., Vega, Reinaldo A.
• Granted Patent: US 9,496,368 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate. The semiconductor includes a first set of sidewall spacers on opposite sidewalls of the gate stack. The semiconductor includes a flowable dielectric layer on the substrate, covering at least a portion of the first set of sidewall spacers. The semiconductor includes a second set of sidewall spacers next to the first set of sidewall spacers covering an upper portion thereof, the second set of sidewall spacers are directly on top of the flowable dielectric layer. The semiconductor includes a contact next to at least one of the second set of sidewall spacers.

Claims

1. A semiconductor structure comprising:

a gate stack on a substrate;

a first set of sidewall spacers on opposite sidewalls of the gate stack;

a flowable dielectric layer on the substrate, covering at least a portion of the first set of sidewall spacers;

a second set of sidewall spacers next to the first set of sidewall spacers covering an upper portion thereof, the second set of sidewall spacers are directly on top of the flowable dielectric layer; and

a contact next to at least one of the second set of sidewall spacers.

2. The semiconductor structure of claim 1, wherein the substrate has a total thickness ranging from about 600 μ

m to about 800 μ

m.

3. The semiconductor structure of claim 1, wherein the flowable dielectric layer has a thickness ranging from about 10% to about 70% of a height of the gate stack.

4. The semiconductor structure of claim 1, wherein the contact is not in direct contact with the first set of sidewall spacers and the second set of sidewall spacers keep the contact away from contacting the first set of sidewall spacers.

5. The semiconductor structure of claim 1, wherein a portion of the contact is formed inside the flowable dielectric layer and is separated from the gate stack by a portion of the flowable dielectric layer.

6. The semiconductor structure of claim 1, wherein the gate stack comprises a gate cap located above and in direct contact with a metal gate.

7. A method comprising:

forming a gate stack on a substrate, the gate stack comprising a gate cap and a gate with the gate cap located above and in direct contact with the gate; and

forming sidewall spacers along opposite sidewalls of the gate stack, each of the sidewall spacers comprising an upper portion and a lower portion, the upper portion having a width greater than the lower portion.

8. The method of claim 7, wherein the upper portion of each of the sidewall spacers has a first section and a second section each made from a different material.

9. The method of claim 8, wherein the first section of the upper portion is a same material as that of the lower portion.

10. The method of claim 7, wherein the upper portion of each of the sidewall spacers has a first section and a second section each made from a different material, the first section of the upper portion is in direct contact with the gate stack and positioned directly above the lower portion.

11. The method of claim 7, further comprising:

forming a contact adjacent to the gate stack, in direct contact with the upper portion of the sidewall spacers, the contact being separated from the lower portion of the sidewall spacers by a flowable dielectric layer.

12. The method of claim 7, wherein the substrate has a total thickness ranging from about 600 μ

m to about 800 μ

m.

13. The method of claim 7, wherein a height of the upper portion of the sidewall spacer is at least 30% of a height of the gate stack.

14. The method of claim 7, wherein a height of the upper portion of the sidewall spacer ranges from about 30% to about 90% of a height of the gate stack.

15. A method comprising:

forming dummy gate stack on a semiconductor substrate;

forming a first set of sidewall spacers on opposite sidewalls of the dummy gate stack;

depositing a first flowable dielectric layer directly on the semiconductor substrate causing the first set of sidewall spacers being embedded inside said first flowable dielectric layer;

exposing an upper portion of the first set of sidewall spacers by recessing the first flowable dielectric layer;

forming a second set of sidewall spacers next to the first set of sidewall spacers covering the upper portion thereof, the second set of sidewall spacers are directly on top of the flowable dielectric layer;

depositing a second flowable dielectric layer on top of the first flowable dielectric covering the dummy gate stack, the first set of sidewall spacers, and the second set of sidewall spacers;

exposing the dummy gate stack by polishing the second flowable dielectric layer;

replacing the dummy gate stack with a metal gate stack;

depositing a third flowable dielectric layer on top of the second flowable dielectric layer covering the metal gate stack, the first set of sidewall spacers, and the second set of sidewall spacers; and

forming a contact adjacent to the metal gate stack in direct contact with the second set of sidewall spacers but not in direct contact with at least a lower portion of the first set of sidewall spacers.

16. The method of claim 15, wherein the semiconductor substrate has a total thickness ranging from about 600 μ

m to about 800 μ

m.

17. The method of claim 15, wherein a portion of the contact is separated from the metal gate stack by at least a portion of the first flowable dielectric layer.

18. The method of claim 15, wherein the metal gate stack comprises a gate cap located above and in direct contact with the metal gate stack.

19. The method of claim 15, wherein exposing the upper portion of the sidewall spacers comprises:

recessing the first flowable dielectric layer thereby exposing at least 30% of a total height of the sidewall spacers.

20. The method of claim 15, wherein exposing the upper portion of the sidewall spacers comprises:

recessing the first flowable dielectric layer to expose between about 30% and about 90% of a total height of the sidewall spacers.