Configurable Logic Circuit Including Dynamic Lookup Table

• US 20160182054A1
• Filed: 12/17/2014
• Published: 06/23/2016
• Est. Priority Date: 12/17/2014
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Lih, Low Yung, Westwick, Alan Lee, Hong, Soh Kok
• Granted Patent: US 9,966,960 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

In some embodiments, a circuit may include a configurable logic module including a multiplexer. The multiplexer may include a plurality of data inputs configured to receive one or more bit strings. Each of the one or more bit strings may correspond to a logic operation. The multiplexer may further include a first control input configured to receive a first input signal, a second control input configured to receive a second input signal, and an output configured to provide an output signal corresponding to a selected logic operation based on the first input signal and the second input signal.

Claims

1. A circuit comprising:

a configurable logic module including;

a multiplexer including;

a plurality of data inputs configured to receive one or more bit strings, each of the one or more bit strings corresponding to a logic operation;

a first control input configured to receive a first input signal;

a second control input configured to receive a second input signal, and

an output configured to provide an output signal corresponding to a selected logic operation based on the first input signal and the second input signal.

2. The circuit of claim 1, wherein the multiplexer further comprises a register configured to store the one or more bit strings, each of the one or more bit strings including multiple bits, the register including a plurality of outputs coupled to the plurality of data inputs.

3. The circuit of claim 1, wherein:

the multiplexer further includes a third control input configured to receive a third input signal; and

the output signal corresponds to the selected logic operation based on the first input signal, the second input signal, and the third input signal.

4. The circuit of claim 3, wherein:

the plurality of data inputs includes eight data inputs; and

the multiplexer is configurable to implement two hundred fifty-six different logic operations.

5. The circuit of claim 1, further comprising a plurality of input multiplexers, each of the plurality of input multiplexers including a plurality of inputs, at least one control input, and an output coupled to one of the first control input and the second control input of the multiplexer.

6. The circuit of claim 1, further comprising a plurality of configurable logic modules including a second configurable logic module coupled to an output of the first configurable logic module.

7. The circuit of claim 6, wherein:

the second configurable logic module includes an output; and

the configurable logic module and the second configurable logic module cooperate to provide a pulse at the output of the second configurable logic module representing a rising edge of an input signal at the at least one selected input.

8. The circuit of claim 1, further comprising:

a plurality of peripheral circuits, at lease one of the plurality of peripheral circuits coupled to a respective one of the plurality of inputs of the configurable logic module; and

a crossbar coupled to an output of the configurable logic module and coupled to the plurality of peripheral circuits and to at least one port driver circuit.

9. A circuit comprising:

a lookup table macrocell including;

a register including a plurality of outputs, the register configured to store one or more bit strings, each of the one or more bit strings configured to represent a logic function; and

a multiplexer including a plurality of inputs coupled to the plurality of outputs of the register, a plurality of control inputs configured to receive input signals, and an output, the multiplexer configured to implement a logic function in response to the input signals and to provide an output signal to the output based on the logic function.

10. The circuit of claim 9, further comprising an interrupt generator circuit coupled to the output of the multiplexer and configured to generate an interrupt signal in response to the output signal.

11. The circuit of claim 9, wherein the register is programmable.

12. The circuit of claim 11, wherein:

each of the one or more bit strings includes eight bits;

the plurality of inputs includes eight inputs;

the plurality of control inputs includes three control inputs; and

the multiplexer is configurable to provide two hundred fifty-six different logic operations.

13. The circuit of claim 9, further comprising logic circuitry coupled to the output of the multiplexer.

14. The circuit of claim 13, wherein the logic circuitry comprises a synchronous register including an input coupled to the output of the multiplexer, a clock input to receive a clock signal, and a synchronous output to provide the output signal synchronized to the clock signal.

15. The circuit of claim 9, wherein the lookup table macrocell further comprises a carry out output to provide a carry out signal.

16. The circuit of claim 15, further comprising a second lookup table macrocell including:

a first input coupled to the output of the lookup table macrocell; and

a second input coupled to the carry out output of the lookup table macrocell.

17. A method comprising:

providing one or more bit strings to a plurality of data inputs of a multiplexer, each of the one or more bit strings representing a logic operation;

applying one or more control input signals to one or more control inputs of the multiplexer to perform a selected logic operation; and

providing an output signal to an output of the multiplexer according to the selected logic operation and based on the one or more control input signals.

18. The method of claim 17, wherein providing the one or more bit strings comprises programming a register with the plurality of bit strings, the register including a plurality of outputs coupled to the plurality of data inputs of the multiplexer.

19. The method of claim 18, wherein the register is programmed by a control circuit to provide one or more selected logic operations.

20. The method of claim 17, wherein applying the one or more control input signals to the one or more control inputs comprises multiplexing a plurality of inputs to provide one of the plurality of inputs to a corresponding one of the one or more control inputs of the multiplexer.