LATERAL/VERTICAL TRANSISTOR STRUCTURES AND PROCESS OF MAKING AND USING SAME

• US 20160184821A1
• Filed: 12/07/2015
• Published: 06/30/2016
• Est. Priority Date: 12/08/2014
• Status: Active Grant

• Current Assignee: Bruker Cellular Analysis, Inc. (Bruker Corporation)
• Original Assignee: Berkeley Lights, Inc. (Bruker Corporation)
• Inventors: Valley, Justin K., Hobbs, Eric D.
• Granted Patent: US 9,908,115 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B01L 2200/0647 Handling flowable solids, e.g. microscopic beads, cells, particles
• CPC Class Codes: B01L 2300/0816 Cards, e.g. flat sample carriers usually with flow in two horizontal directions
• CPC Class Codes: B01L 2300/0819 Microarrays; Biochips
• CPC Class Codes: B01L 2400/0415 electrical forces, e.g. electrokinetic
• CPC Class Codes: B01L 2400/0424 Dielectrophoretic forces
• CPC Class Codes: B01L 3/502707 characterised by the manufacture of the container or its components by shaping or joining plastic parts B29C59/00, B29C65/00; by laminating B32B37/00; manufacture of microstructural devices in general B81C
• CPC Class Codes: B01L 3/502715 characterised by interfacing components, e.g. fluidic, electrical, optical or mechanical interfaces
• CPC Class Codes: B01L 3/50273 characterised by the means or forces applied to move the fluids micropumps F04B19/006, of the membrane type F04B43/043
• CPC Class Codes: B01L 3/502761 specially adapted for handling suspended solids or molecules independently from the bulk fluid flow, e.g. for trapping or sorting beads, for physically stretching molecules investigating characteristics of particles G01N15/00
• CPC Class Codes: B03C 5/005 Dielectrophoresis, i.e. dielectric particles migrating towards the region of highest field strength
• CPC Class Codes: B03C 5/026 using open-gradient differential dielectric separation, i.e. using electrodes of special shapes for non-uniform field creation, e.g. Fluid Integrated Circuit [FIC]
• CPC Class Codes: H01L 27/0823 including vertical bipolar transistors only
• CPC Class Codes: H01L 27/14681 Bipolar transistor imagers
• CPC Class Codes: H01L 29/732 Vertical transistors

Abstract

A microfluidic device can include a base an outer surface of which forms one or more enclosures for containing a fluidic medium. The base can include an array of individually controllable transistor structures each of which can comprise both a lateral transistor and a vertical transistor. The transistor structures can be light activated, and the lateral and vertical transistors can thus be photo transistors. Each transistor structure can be activated to create a temporary electrical connection from a region of the outer surface of the base (and thus fluidic medium in the enclosure) to a common electrical conductor. The temporary electrical connection can induce a localized electrokinetic force generally at the region, which can be sufficiently strong to move a nearby micro-object in the enclosure.

Claims

1. A microfluidic device comprising:

an enclosure having a microfluidic structure and a base,

wherein the base comprises a common electrical conductor,

wherein the microfluidic structure and an outer surface of the base together define a flow path within the enclosure, and

wherein the base comprises an array of transistor structures, each said transistor structure in the array comprising a lateral bipolar transistor connecting a corresponding region of the outer surface of the base to the common conductor.

2. The microfluidic device of claim 1, wherein each said transistor structure in the array further comprises a vertical bipolar transistor connecting the corresponding region of the outer surface of the base to the common conductor.

3. The microfluidic device of claim 1, wherein each said transistor structure in the array comprises a collector region, a base region, and an emitter region,

wherein the base region surrounds the emitter region,

wherein the collector region surrounds the base region,

wherein the base region has a lateral width that is between about 10 nm and about 400 nm,

wherein each said transistor structure in the array is physically separated from adjacent transistor structures in the array by trenches, and

wherein an electrically insulative material is disposed in the trenches.

5. The microfluidic device of claim 3, wherein the base region has a lateral width that is between about 200 nm and about 300 nm.

6. The microfluidic device of claim 3, wherein the base region has a vertical thickness equal to or greater than the lateral width of the base region and the collector region has a vertical thickness equal to or greater than the lateral width of the collector region.

7. The microfluidic device of claim 6, wherein the vertical thickness of the base region is about two to four times greater than the lateral width of the base region and the vertical thickness of the collector region is about two to ten times greater than the lateral width of the collector region.

8. The microfluidic device of claim 6, wherein the vertical thickness of the base region is about three to four times greater than the lateral width of the base region and the vertical thickness of the collector region is about four to eight times greater than the lateral width of the collector region.

9. The microfluidic device of claim 6, wherein the vertical thickness of the base region is about 3.5 times greater than the lateral width of the base region and the vertical thickness of the collector region is about six times greater than the lateral width of the collector region.

10. The microfluidic device of claim 3, wherein the base region comprises a p-type dopant and the collector and emitter regions each comprise an n-type dopant.

12. The microfluidic device of claim 1, wherein the common conductor comprises an N+ semiconductor substrate upon which the array of transistor structures rests.

14. The microfluidic device of claim 12 or 13, wherein the N+ semiconductor substrate has a resistivity of about 0.025 ohm−

cm to about 0.050 ohm−

cm.

15. The microfluidic device of claim 3, wherein the collector region has a lateral width that is between about 100 nm and about 1000 nm.

16. The microfluidic device of claim 3, wherein the collector region has a lateral width that is between about 600 nm and about 750 nm.

23. The microfluidic device of claim 3, wherein the collector region has a resistivity of about 5 ohm−

cm to about 10 ohm−

cm.

24. The microfluidic device of claim 3, wherein a vertical thickness of the emitter region is about 10 nm to about 500 nm, wherein a vertical thickness of the base region is about 6 to 12 times greater than a vertical thickness of the emitter region, and wherein a vertical thickness of the collector region is about 3 to 6 times greater than a vertical thickness of the base region.

25. The microfluidic device of claim 24, wherein a vertical thickness of the emitter region is about 50 nm to about 150 nm.

30. The microfluidic device of claim 1, wherein a pitch of the transistor structures of the array is about 1000 nm to about 20,000 nm.

33. The microfluidic device of claim 3, wherein a vertical depth of the trench is at least 10% greater than a combined vertical depth of the collector, base, and emitter regions.

34. The microfluidic device of claim 3, wherein a vertical depth of the trench is about 2,000 nm to about 11,000 nm and a lateral width of the trench is about 100 nm to about 1000 nm.

37. The microfluidic device of claim 3, further comprising a dielectric border disposed on the outer surface of the base between adjacent pairs of the transistor structures of the array, wherein the border overlays a perimeter portion of the emitter region of each said transistor structure of the array but comprises windows exposing an interior portion of the emitter region.

39. The microfluidic device of claim 37, wherein a vertical thickness of the border is about 750 nm to about 2,000 nm.

40. The microfluidic device of claim 37, wherein the dielectric border overlays the perimeter portion of the emitter region by about 10 nm to about 200 nm.

41. The microfluidic device of claim 1, wherein the microfluidic structure and the base together further define a holding pen, and wherein the holding pen is connected to the flow path.

42. The microfluidic device of claim 41, wherein the flow path comprises a fluidic channel, and wherein the holding pen is connected to the fluidic channel.

45. The microfluidic device of claim 1, wherein:

the transistor structures of the array connect different regions of the outer surface of the base to the common conductor, and

the regions of the outer surface of the base are disposed to contact directly fluidic medium in the flow path.

46. The microfluidic device of claim 45 further comprising a biasing electrode, wherein the flow path is disposed between the biasing electrode and the common electrical conductor of the base.

54. A method of moving a micro-object in a fluidic medium in the microfluidic device of claim 46, the method comprising:

providing biasing power to the biasing electrode and the common electrical conductor of the base; and

activating a first of the transistor structures at a first of the regions of the outer surface of the base,

wherein said activating induces a first current flow in at least a lateral bipolar transistor of the first transistor structure and creates an eletrokinetic force in the vicinity of the activated first transistor structure sufficient to move a nearby micro-object in the flow path.

59. The method of claim 54, wherein the activating also induces a second current flow in a vertical transistor of the activated first transistor structure.

60. The method of claim 59, wherein the second current flow enhances the electrokinetic force.

62. The method of claim 59, wherein a current density of the first current flow in the lateral transistor is at least 1.5 times greater than a current density of the second current flow in the vertical transistor of the activated first transistor structure.

63. The method of claim 54, wherein the activating comprises directing a beam of light onto the base region of the first transistor structure.

70. The method of claim 54, wherein the providing comprises providing the biasing power with a peak-to-peak voltage of about 1 Vppk to about 50 Vppk.

71. The method of claim 54, wherein the providing comprises providing the biasing power at a frequency of about 100 kHz to about 10 MHz.

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