DYNAMIC HIERARCHICAL PERFORMANCE BALANCING OF COMPUTATIONAL RESOURCES

• US 20160187944A1
• Filed: 12/26/2014
• Published: 06/30/2016
• Est. Priority Date: 12/26/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Eastep, Jonathan M., Sharapov, Ilya, Greco, Richard J., Sylvester, Steve S., Lombard, David N.
• Granted Patent: US 10,466,754 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 9/5061 Partitioning or combining of resources
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods may provide a set of networked computational resources such as nodes that may be arranged in a hierarchy. A hierarchy of performance balancers receives performance samples from the computational resources beneath them and uses the performance samples to conduct a statistical analysis of variations in their performance. In one embodiment, the performance balancers steer power from faster resources to slower resources in order to enhance their performance, including in parallel processing.

Claims

1. A method of controlling performance among computational resources, comprising:

collecting a plurality of performance samples from each of a plurality of computational resources;

computing a statistic from the plurality of performance samples for each computing resource of the plurality of computational resources; and

adjusting an operating parameter of at least one computational resource of the plurality of computational resources, wherein adjusting the operating parameter causes the performance of the at least one computational resource to change.

2. The method of claim 1, wherein the operating parameter includes an operating frequency of at least one core and/or at least one processor.

3. The method of claim 1, wherein the operating parameter includes an amount of power supplied to at least one computational resource of the plurality of computational resources, and wherein the method further includes steering power from at least one relatively faster computational resource of the plurality of computational resources to at least one relatively slower computational resource of the plurality of computational resources.

4. The method of claim 3, wherein steering is based on the statistic, and wherein the statistic is a measure of a skew derived from the plurality of performance samples.

5. The method of claim 1, wherein the plurality of computational resources includes one or more of a core, a processor, a node, a cabinet, a row, a cluster, or a grid.

6. The method of claim 4, further including:

arranging the plurality of computational resources in a list from fastest to slowest;

successively pairing a relatively faster computational resource of the plurality of computational resources on the list with a relatively slower computational resource of the plurality of computational resources on the list to form pairs; and

steering electrical power from the relatively faster computational resource within each of the pairs to the relatively slower computational resource within each of the pairs.

7. The method of claim 1, wherein performance variations within a group of computational resources of the plurality of computational resources are reduced.

8. The method of claim 5, wherein the plurality of computational resources are arrayed in a hierarchy including a plurality of levels, wherein a plurality of performance balancers mediate between the plurality of levels, and wherein at least one performance balancer of the plurality of performance balancers issues performance commands to computational resources arrayed in the hierarchy at a first level of the plurality of levels and receives performance data back from the computational resources arrayed in the hierarchy at a second level of the plurality of levels.

9. The method of claim 8, wherein the plurality of performance balancers form a hierarchy of performance balancers, wherein relatively upper level performance balancers issue performance commands to relatively lower level performance balancers beneath the relatively upper level performance balancers in the hierarchy of performance balancers, wherein relatively lower level performance balancers send data to relatively upper level performance balancers above the relatively lower performance balancers in the hierarchy, and wherein the data is performance data of a level of the hierarchy of computational resources, and wherein the commands include one or more of frequency settings or power budgets.

10. The method of claim 9, wherein the data is sent up the hierarchy of performance balancers from a given level of the hierarchy of computational resources only when the given level has a stable performance configuration, and wherein the commands are sent down from a performance balancer only after the data has been sent to the performance balancer.

11. The method of claim 9, wherein the performance samples are collected at times that vary with the level of the hierarchy of computational resources from which the performance samples are collected.

12. An apparatus to vary performance among computational resources, comprising:

a plurality of computational resources that are to be connected to one another;

logic, implemented at least partly in fixed-functionality hardware, to;

collect a plurality of performance samples from each computational resource of the plurality of computational resources;

compute a statistic from the plurality of performance samples for each computational resource of the plurality of computational resources; and

adjust an operating parameter of at least one computational resource of the plurality of computational resources based on the statistic.

13. The apparatus of claim 12, wherein the operating parameter is to include one or more of power or frequency.

14. The apparatus of claim 12, wherein the plurality of computational resources is to include one or more of a core, a processor, a node, a cabinet, a row, a cluster, or a grid.

15. The apparatus of claim 14, wherein the computational resources are to be arrayed in a hierarchy including a plurality of levels, wherein a plurality of performance balancers are to mediate between the plurality of levels, wherein at least one performance balancer of the plurality of performance balancers is to issue performance commands to computational resources to be arrayed in the hierarchy at a first level of the plurality of levels and is to receive performance data back from the computational resources to be arrayed in the hierarchy at a second level of the plurality of levels.

16. The apparatus of claim 15, wherein the plurality of performance balancers form a hierarchy of performance balancers, wherein relatively upper level performance balancers are to issue performance commands to relatively lower level performance balancers beneath the relatively upper level performance balancers in the hierarchy of performance balancers, wherein relatively lower level performance balancers are to send data to relatively upper level performance balancers above the relatively lower performance balancers in the hierarchy, and wherein the data is to be performance data of a level of the hierarchy of computational resources.

17. The apparatus of claim 15, wherein the performance commands are to include one or more of frequency settings or power budgets.

18. The apparatus of claim 12, wherein the logic is to:

arrange the plurality of computational resources in a list from fastest to slowest;

successively pair off a relatively faster computational resource of the plurality of computing resources on the list with a relatively slower computational resource of the plurality of computing resources on the list to form pairs; and

steer electrical power from the relatively faster computational resource within each of the pairs to the relatively slower computational resource within each of the pairs.

19. At least one computer readable storage medium, wherein the instructions, when executed, cause a computing device to:

collect a plurality of performance samples from each of a plurality of connected computational resources;

compute a statistic from the plurality of performance samples for each computational resource of the plurality of computational resources; and

adjust an operating parameter of at least one computational resource of the plurality of computational resources based on the statistic.

20. The at least one computer readable storage medium of claim 19, wherein the operating parameter is include one or more of power or frequency.

21. The at least one computer readable storage medium of claim 19, wherein the plurality of computational resources is to include one or more of a core, a processor, a node, a cabinet, a row, a cluster, or a grid.

22. The at least one computer readable storage medium of claim 19, wherein the computational resources are to be arrayed in a hierarchy including a plurality of levels, and wherein the instructions, when executed, cause the computing device to:

mediate between the plurality of levels of the hierarchy;

issue performance commands to computational resources to be arrayed in the hierarchy at a first level of the plurality of levels; and

receive performance data back from the computational resources arrayed in the hierarchy at a second level of the plurality of levels.

23. The at least one computer readable storage medium of claim 19, wherein the instructions, when executed, cause a computing device to:

form a hierarchy of performance balancers from a plurality of performance balancers;

direct relatively upper level performance balancers to issue performance commands to relatively lower level performance balancers beneath the relatively upper level performance balancers in the hierarchy of performance balancers; and

direct the relatively lower level performance balancers to send data to the relatively upper level performance balancers above the relatively lower performance balancers in the hierarchy.

24. The at least one computer readable storage medium of claim 23, wherein the performance commands are to include one or more of frequency settings or power budgets.

25. The at least one computer readable storage medium of claim 19, wherein the instructions, when executed, cause a computing device to:

arrange the plurality of computational resources in a list from fastest to slowest;

successively pair off a relatively faster computational resource of the plurality of computing resources on the list with a relatively slower computational resource of the plurality of computing resources on the list to form pairs of a relatively faster computational resource and a relatively slower computational resource; and

steer electrical power from the relatively faster computational resource within each of the pairs to the relatively slower computational resource within each of the pairs.