FAULT TOLERANT AUTOMATIC DUAL IN-LINE MEMORY MODULE REFRESH

• US 20160188414A1
• Filed: 12/24/2014
• Published: 06/30/2016
• Est. Priority Date: 12/24/2014
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: JAYAKUMAR, SARATHY, KUMAR, MOHAN J.
• Application Number:
  US14/583,037
• Publication Number:
  US 20160188414A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G11C 14/0036 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

Methods and apparatus to fault tolerant Automatic DIMM (Dual In-line Memory Module) Refresh or ADR are described. In an embodiment, a processor includes non-volatile memory to store data from one or more volatile buffers of the processor. The data from the one or more volatile buffers of the processor are stored into the non-volatile memory in response to occurrence of an event that is to lead to a system reset or shut down. Other embodiments are also disclosed and claimed.

Claims

1. An apparatus comprising:

a processor including non-volatile memory to store data from one or more volatile buffers of the processor; and

logic to cause storage of the data from the one or more volatile buffers of the processor into the non-volatile memory in response to occurrence of an event that is to lead to a system reset or shut down.

2. The apparatus of claim 1, further comprising a Power Control Unit (PCU) to generate a signal to indicate occurrence of the event.

3. The apparatus of claim 1, further comprising one or more sensors to detect occurrence of the event.

4. The apparatus of claim 1, wherein the processor and the non-volatile memory are to be coupled to the same power rail.

5. The apparatus of claim 1, further comprising one or more capacitors, coupled to the non-volatile memory, to increase an amount of time the non-volatile memory remains operational after occurrence of the event.

6. The apparatus of claim 1, comprising logic to block further transactions in response to occurrence of the event.

7. The apparatus of claim 1, wherein the logic is to update a flag to indicate start of storage of the data from the one or more volatile buffers of the processor into the non-volatile memory.

8. The apparatus of claim 1, wherein the logic is to update a flag to indicate completion of storage of the data from the one or more volatile buffers of the processor into the non-volatile memory.

9. The apparatus of claim 1, wherein the event corresponds to an Alternating Current (AC) power failure.

10. The apparatus of claim 1, wherein the processor is to comprise the logic.

11. The apparatus of claim 1, wherein the one or more volatile buffers are to comprise one or more non-volatile DIMMs (Dual Inline Memory Modules).

12. The apparatus of claim 1, wherein the non-volatile memory is to comprise one or more of:

nanowire memory, Ferro-electric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM), flash memory, Spin Torque Transfer Random Access Memory (STTRAM), Resistive Random Access Memory, byte addressable 3-Dimensional Cross Point Memory, Phase Change Memory (PCM).

13. The apparatus of claim 1, wherein one or more of the processor having one or more processor cores, the non-volatile memory, and the logic are on a same integrated circuit die.

14. A method comprising:

storing data from one or more volatile buffers of a processor in non-volatile memory of the processor; and

causing storage of the data from the one or more volatile buffers of the processor into the non-volatile memory in response to occurrence of an event that is to lead to a system reset or shut down.

15. The method of claim 14, further comprising a Power Control Unit (PCU) generating a signal to indicate occurrence of the event.

16. The method of claim 14, further comprising one or more sensors detecting occurrence of the event.

17. The method of claim 14, wherein the processor and the non-volatile memory are coupled to the same power rail.

18. The method of claim 14, wherein one or more capacitors are coupled to the non-volatile memory to increase an amount of time the non-volatile memory remains operational after occurrence of the event.

19. The method of claim 14, comprising blocking further transactions in response to occurrence of the event.

20. The method of claim 14, further comprising updating a flag to indicate start of storage of the data from the one or more volatile buffers of the processor into the non-volatile memory.

21. The method of claim 14, further comprising updating a flag to indicate completion of storage of the data from the one or more volatile buffers of the processor into the non-volatile memory.

22. The method of claim 14, wherein the event corresponds to an Alternating Current (AC) power failure.