COST-AWARE PAGE SWAP AND REPLACEMENT IN A MEMORY

• US 20160188490A1
• Filed: 12/26/2014
• Published: 06/30/2016
• Est. Priority Date: 12/26/2014
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Samih, Ahmad A.
• Application Number:
  US14/583,343
• Publication Number:
  US 20160188490A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 12/127 using additional replacement algorithms
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

Memory eviction that recognizes not all evictions have an equal cost on system performance. A management device keeps a weight and/or a count associated with each portion of memory. Each memory portion is associated with a source agent that generates requests to the memory portion. The management device adjusts the weight by a cost factor indicating a latency impact that could occur if the evicted memory portion is again requested after being evicted. The latency impact is a latency impact for the associated source agent to replace the memory portion. In response to detecting an eviction trigger for the memory device, the management device can identify a memory portion having a most extreme weight, such as a highest or lowest value weight. The management device replaces the identified memory portion with a memory portion that triggered the eviction.

Claims

1. A method for managing eviction from a memory device, comprising:

initializing a count for one of multiple memory portions in a memory device, including associating the count with a source agent that accesses the one memory portion;

adjusting the count based on access to the one memory portion by the associated source agent;

adjusting the count based on a dynamic cost factor for the associated source agent, where the dynamic cost factor represents a latency impact to performance of the source agent to replace the memory portion; and

comparing the count to counts for others of the multiple portions to determine which memory portion to evict in response to an eviction trigger for the memory device.

2. The method of claim 1, wherein the memory device comprises a main memory resource for a host system.

3. The method of claim 2, wherein the comparing comprise comparing with a memory controller device.

4. The method of claim 2, wherein initializing the count comprises initializing the count in response to receiving a request from a lower-level memory requesting data.

5. The method of claim 1, wherein comparing the count further comprises identifying for eviction one of the multiple memory portions having a lowest cost.

6. The method of claim 5, wherein the cost factor includes a replacement cost factor 1/N added to a least recently used (LRU) factor, where N is a number of parallel requests currently pending for the associated source agent.

7. The method of claim 1, wherein the cost factor is dynamically adjustable by a scaling factor to provide more or less weight to the cost factor.

8. A memory management device, comprising:

a queue to store requests for access to a memory device managed by the memory management device;

an eviction table to store a weight associated with each of multiple memory portions of the memory device, each of the multiple memory portions having an associated source agent that generates requests for data stored in the memory portion, wherein each weight is factored based on access history for the memory portion as well as a cost factor that indicates a latency impact on the associated source agent to replace the memory portion; and

an eviction processor configured to initialize a count for one of the memory portions;

adjust the count based on access to the one memory portion by the associated source agent;

adjust the count based on a dynamic cost factor for the associated source agent; and

compare the count to counts for others of the multiple memory portions to determine which memory portion to evict in response to an eviction trigger for the memory device.

9. The memory management device of claim 8, wherein the memory device comprises a DRAM (dynamic random access memory) resource for a host system.

10. The memory management device of claim 9, wherein the eviction processor comprises a processor of a memory controller device.

11. The memory management device of claim 9, wherein the DRAM is a highest level memory of a multilevel memory (MLM) system, wherein the eviction processor is to detect the eviction trigger in response to a page fault occurring in response to servicing a request from a cache of the MLM.

12. The memory management device of claim 8, wherein the eviction processor is to identify the memory portion having a lowest cost to evict.

13. The memory management device of claim 12, wherein the cost factor includes a replacement cost factor 1/N added to a least recently used (LRU) factor, where N is a number of parallel requests currently pending in the queue for the associated source agent.

14. The memory management device of claim 8, wherein the cost factor is dynamically adjustable by a scaling factor to provide more or less weight to the cost factor.

17. The memory management device of claim 9, wherein the SDRAM is a highest level memory of a multilevel memory (MLM) system, wherein the eviction processor is to detect the eviction trigger in response to a page fault occurring in response to servicing a request from a cache of the MLM.

15. An electronic device with a memory subsystem, comprising:

an SDRAM (synchronous dynamic random access memory) including a memory array to store multiple memory portions, each of the multiple memory portions having an associated source agent that generates requests for data stored in the SDRAM, wherein each weight is computed based on access history for the memory portion as well as a cost factor that indicates a latency impact on the associated source agent to replace the memory portion; and

a memory controller to control access to the SDRAM, the memory controller including

a queue to store requests for access to the SDRAM;

an eviction table to store a weight associated with each of multiple memory portions; and

an eviction processor configured to initialize a count for one of the memory portions;

adjust the count based on access to the one memory portion by the associated source agent;

adjust the count based on a dynamic cost factor for the associated source agent; and

compare the count to counts for others of the multiple memory portions to determine which memory portion to evict in response to an eviction trigger for the memory device; and

a touchscreen display coupled to generate a display based on data accessed from the SDRAM.

16. The electronic device of claim 15, wherein the memory controller comprises a memory controller circuit integrated onto a host processor system on a chip (SoC).

18. The electronic device of claim 15, wherein the eviction processor is to identify for eviction the memory portion having a lowest count.

19. The electronic device of claim 15, wherein the cost factor includes a replacement cost factor 1/N added to a least recently used (LRU) factor, where N is a number of parallel requests currently pending in the queue for the associated source agent.

20. The electronic device of claim 15, wherein the cost factor is dynamically adjustable by a scaling factor to provide more or less weight to the cost factor.