ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR DRIVING THE SAME

• US 20160189603A1
• Filed: 07/08/2015
• Published: 06/30/2016
• Est. Priority Date: 12/24/2014
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Lee, Joonhee, Kim, Sunghoon, Park, Jongmin
• Granted Patent: US 9,953,565 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0413 Details of dummy pixels or dummy lines in flat panels
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0202 Addressing of scan or signal lines
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0204 Compensation of DC component across the pixels in flat panels
• CPC Class Codes: G09G 2320/0219 Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes

Abstract

An organic light emitting diode display and a method for driving the same are disclosed. The organic light emitting diode display includes a display panel including a plurality of pixels, a display panel driver configured to drive signal lines of the display panel, and a timing controller configured to divide one frame into a plurality of subframes, divide data of an input image at each bit, map the data of the input image to the plurality of subframes, control an operation of the display panel driver, and adjust data addressing speeds of the plurality of subframes for adjusting the emission times of the upper and lower display lines of the display panel differently.

Claims

1. An organic light emitting diode display comprising:

a display panel including a plurality of pixels;

a display panel driver configured to drive signal lines of the display panel; and

a timing controller configured to divide one frame into a plurality of subframes, divide data of an input image at each bit, map the data of the input image to the plurality of subframes, control an operation of the display panel driver, and adjust data addressing speeds of the plurality of subframes for adjusting emission times of upper and lower display lines of the display panel differently.

2. The organic light emitting diode display according to claim 1, wherein the timing controller adjusts the data addressing speed of at least one subframe of the plurality of subframes differently from a previously determined reference value.

3. The organic light emitting diode display according to claim 1, wherein when a high potential power voltage for driving the pixels is applied to the display panel from an upper side of the display panel and data addressing is sequentially performed from the upper side to a lower side of the display panel in a sequential line manner, the timing controller reduces the data addressing speed as it goes from a first subframe to a last subframe of the one frame,

wherein a most significant bit (MSB) of the data will be mapped to the first subframe, and a least significant bit (LSB) of the data will be mapped to the last subframe.

4. The organic light emitting diode display according to claim 1, wherein when a high potential power voltage for driving the pixels is applied to the display panel from a lower side of the display panel and data addressing is sequentially performed from an upper side to the lower side of the display panel in a sequential line manner, the timing controller increases the data addressing speed as it goes from a first subframe to a last subframe of the one frame,

wherein a most significant bit (MSB) of the data will be mapped to the first subframe, and a least significant bit (LSB) of the data will be mapped to the last subframe.

5. The organic light emitting diode display according to claim 1, wherein the timing controller includes a multiplexer configured to receive a plurality of gate shift clocks having different pulse periods and selectively outputs one of the plurality of gate shift clocks to the display panel driver at start timing of each subframe.

6. The organic light emitting diode display according to claim 1, wherein a dummy subframe is further arranged after a last subframe in the one frame, and

wherein a length of the dummy subframe at an upper display line of the display panel is different from a length of the dummy subframe at a lower display line of the display panel.

7. The organic light emitting diode display according to claim 6, wherein the display panel driver applies a data voltage, which causes the pixels not to emit light, to the display panel during the dummy subframe.

8. A method for driving an organic light emitting diode display including a display panel including a plurality of pixels and a display panel driver driving signal lines of the display panel, the method comprising:

dividing one frame into a plurality of subframes, dividing data of an input image at each bit, and mapping the data of the input image to the plurality of subframes; and

controlling an operation of the display panel driver and adjusting data addressing speeds of the plurality of subframes for adjusting emission times of upper and lower display lines of the display panel differently.

9. The method according to claim 8, wherein the adjusting of the data addressing speeds includes adjusting the data addressing speed of at least one subframe of the plurality of subframes differently from a previously determined reference value.

10. The method according to claim 8, wherein when a high potential power voltage for driving the pixels is applied to the display panel from an upper side of the display panel and data addressing is sequentially performed from the upper side to a lower side of the display panel in a sequential line manner, the adjusting of the data addressing speeds includes reducing the data addressing speed from a first subframe to a last subframe of the one frame,

wherein a most significant bit (MSB) of the data will be mapped to the first subframe, and a least significant bit (LSB) of the data will be mapped to the last subframe.

11. The method according to claim 8, wherein when a high potential power voltage for driving the pixels is applied to the display panel from a lower side of the display panel and data addressing is sequentially performed from an upper side to the lower side of the display panel in a sequential line manner, the adjusting of the data addressing speeds includes increasing the data addressing speed from a first subframe to a last subframe of the one frame,

wherein a most significant bit (MSB) of the data will be mapped to the first subframe, and a least significant bit (LSB) of the data will be mapped to the last subframe.

12. The method according to claim 8, wherein the adjusting of the data addressing speeds includes receiving a plurality of gate shift clocks having different pulse periods and selectively outputting one of the plurality of gate shift clocks to the display panel driver at start timing of each subframe.

13. The method according to claim 8, wherein a dummy subframe is further arranged after a last subframe in the one frame, and

wherein a length of the dummy subframe at an upper display line of the display panel is different from a length of the dummy subframe at a lower display line of the display panel.

14. The method according to claim 13, further comprising applying a data voltage, which causes the pixels not to emit light, to the display panel during the dummy subframe.