SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM
First Claim
1. A semiconductor storage device comprising:
- a memory string including a memory cell;
a bit line electrically connected to one end of the memory string; and
a sense amplifier electrically connected to the bit line, whereinthe sense amplifier comprises;
a first transistor, one end of which is connected to a first node on an electric current path of the bit line, and another end of which is electrically connected to a second node;
a second transistor electrically connected between the second node and a sense node; and
a third transistor, a gate of which is connected to the first node, and the third transistor being electrically connected between the second node and a third node whose voltage can be adjusted.
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Accused Products
Abstract
A semiconductor storage device has a memory string including a memory cell, a bit line electrically connected to one end of the memory string, and a sense amplifier electrically connected to the bit line. The sense amplifier has a first transistor, one end of which is connected to a first node on an electric current path of the bit line, and another end of which is electrically connected to a second node, a second transistor electrically connected between the second node and a sense node, and a third transistor, a gate of which is connected to the first node, and the third transistor being electrically connected between the second node and a third node whose voltage can be adjusted.
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Citations
20 Claims
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1. A semiconductor storage device comprising:
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a memory string including a memory cell; a bit line electrically connected to one end of the memory string; and a sense amplifier electrically connected to the bit line, wherein the sense amplifier comprises; a first transistor, one end of which is connected to a first node on an electric current path of the bit line, and another end of which is electrically connected to a second node; a second transistor electrically connected between the second node and a sense node; and a third transistor, a gate of which is connected to the first node, and the third transistor being electrically connected between the second node and a third node whose voltage can be adjusted. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A memory system comprising:
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a semiconductor storage device having a memory string including a memory cell;
a bit line electrically connected to one end of the memory string;
a sense amplifier electrically connected to the bit line; and
an internal controller configured to control the operation of the sense amplifier, in which the sense amplifier comprises;
a first transistor, one end of which is connected to a first node on an electric current path of the bit line, and another end of which is electrically connected to a second node;
a second transistor electrically connected between the second node and a sense node; and
a third transistor, a gate of which is connected to the first node, and which third transistor is electrically connected between the second node and a third node whose voltage can be adjusted; andan external controller configured to control data writing to the semiconductor storage device and data reading from the semiconductor storage device, wherein based on an instruction from the external controller, the internal controller selects one of a first sensing manner for passing an electric current to the third node from the bit line through the first transistor and the third transistor and thereafter passing an electric current to the third node from the sense node through the second transistor and the third transistor during reading from the memory cell and a second sensing manner for making a voltage of the second node stable and thereafter passing an electric current to the bit line from the sense node through the second transistor and the first transistor during reading from the memory cell. - View Dependent Claims (20)
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Specification