METHODS FOR FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES FABRICATED BY THE SAME

• US 20160190004A1
• Filed: 12/10/2015
• Published: 06/30/2016
• Est. Priority Date: 12/26/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Jae-Hwang Sim
• Inventors: LIM, Joon-Sung, Song, Min-Sung, SIM, Jae-Hwang
• Granted Patent: US 9,761,603 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

sequentially forming an etch target layer, a lower mold layer, and an intermediate mold layer on a substrate, the etch target layer including a separation region;

forming first mold patterns on the intermediate mold layer;

forming first spacers on sidewalls of the first mold patterns;

etching the intermediate mold layer using the first spacers as etch masks to form second mold patterns;

forming second spacers on sidewalls of the second mold patterns;

etching the lower mold layer using the second spacers as etch masks to form third mold patterns;

forming a fourth mold pattern that at least partially covers at least one of the third mold patterns, the fourth mold pattern vertically overlapping the separation region;

etching the etch target layer using the fourth mold pattern and ones of the third mold patterns that are exposed by the fourth mold pattern as etch masks to form insulating patterns; and

forming conductive lines in spaces between the insulating patterns.

2. The method of claim 1, wherein the substrate includes a cell array region and a peripheral circuit region,

wherein the separation region is on the cell array region,

wherein the fourth mold pattern includes a plurality of fourth mold patterns, and

wherein a one of the fourth mold patterns that is on the peripheral circuit region exposes a portion of the etch target layer that is on the peripheral circuit region.

3. The method of claim 2, wherein the first, second and third mold patterns are formed on the cell array region.

4. The method of claim 2, wherein forming the first mold patterns comprises:

forming an upper mold layer on the intermediate mold layer;

forming photoresist patterns on the upper mold layer, the photoresist patterns covering the upper mold layer of the peripheral circuit region but exposing portions of the upper mold layer of the cell array region; and

etching the upper mold layer using the photoresist patterns as etch masks to form the first mold patterns on the cell array region.

5. The method of claim 2, wherein the portion of the lower mold layer that is on the peripheral circuit region is completely etched when the third mold patterns are formed.

6. The method of claim 2, wherein forming the fourth mold patterns comprises:

forming a preliminary mold layer on the third mold patterns;

forming photoresist patterns on the preliminary mold layer; and

etching the preliminary mold layer using the photoresist patterns as etch masks to form fourth mold patterns,

wherein the photoresist pattern on the cell array region vertically overlaps the separation region.

7. The method of claim 1, wherein the third mold patterns include a first extension pattern and a second extension pattern that extend in parallel to each other in one direction, and

wherein one sidewall of the fourth mold pattern is disposed between the first extension pattern and the second extension pattern.

8. The method of claim 7, wherein etching the etch target layer to form the insulating patterns comprises:

etching a portion of the etch target layer, which is exposed by the fourth mold pattern between the first and second extension patterns, to form a dummy trench.

9. The method of claim 8, wherein a width of a portion of the dummy trench is substantially equal to a maximum width of the first spacer, and

wherein a width of another portion of the dummy trench is smaller than the maximum width of the first spacer.

10. The method of claim 8, wherein forming the conductive lines comprises:

forming a dummy interconnection in the dummy trench,

wherein the dummy interconnection is between the separation region and a first of the insulating patterns that is adjacent the separation region.

11. The method of claim 1, further comprising:

forming a first mask layer on the intermediate mold layer before forming the first mold patterns; and

etching the first mask layer using the first spacers as etch masks to form first mask patterns,

wherein the first mask patterns are also used as etch masks when the intermediate mold layer is etched.

12. The method of claim 1, wherein a width of at least one of the first mold patterns is about three times a maximum width of one of the first spacers.

13. The method of claim 1, wherein a distance between adjacent ones of the first mold patterns is about five times a maximum width of the one of the first spacers.

14. The method of claim 1, wherein a width of at least one of the second mold patterns and a width of at least one of the third mold patterns are substantially equal to a maximum width of one of the first spacers.

15. The method of claim 1, wherein a distance between adjacent ones of the second mold patterns is about three times a maximum width of one of the first spacers.

16. The method of claim 1, wherein a distance between adjacent ones of the third mold patterns is substantially equal to a maximum width of one of the first spacers.

17. The method of claim 1, wherein a maximum width of at least one of the second spacers is substantially equal to a maximum width of one of the first spacers.

18-50. -50. (canceled)

51. A method for fabricating a semiconductor device, the method comprising:

forming an etch target layer on a substrate, the etch target layer including a separation region;

forming a lower mold layer on the etch target layer opposite the substrate;

forming an intermediate mold layer on the lower mold layer opposite the etch target layer;

forming first mold patterns on the intermediate mold layer;

forming first spacers on sidewalls of the first mold patterns, wherein a first of the first spacers that is on a sidewall of a first of the first mold patterns has a maximum width that is about one third a maximum width of the first of the first mold patterns;

etching the intermediate mold layer using the first spacers as etch masks to form second mold patterns, wherein a first of the second mold patterns has a width that is substantially equal to the maximum width of the first of the first spacers;

forming second spacers on sidewalls of the second mold patterns, wherein a first of the second spacers has a width that is substantially equal to the maximum width of the first of the first spacers;

etching the lower mold layer using at least the second spacers as etch masks to form third mold patterns;

etching the etch target layer using at least some of the third mold patterns as etch masks to form etch target layer patterns; and

forming conductive lines in spaces between the etch target layer patterns.

52. The method of claim 51, wherein a distance between adjacent ones of the first mold patterns is about five times a maximum width of the first of the first spacers, and

wherein a distance between adjacent ones of the second mold patterns is about three times a maximum width of the first of the first spacers.

53. The method of claim 51, further comprising after forming the third mold patterns:

forming a fourth mold pattern on at least one of the third mold patterns, the fourth mold pattern vertically overlapping the separation region,

wherein etching the etch target layer using at least some of the third mold patterns as etch masks to form etch target layer patterns comprises etching the etch target layer using the fourth mold pattern and ones of the third mold patterns that are exposed by the fourth mold pattern as etch masks to form the etch target layer patterns.

54-57. -57. (canceled)