ARRAY SUBSTRATE AND DISPLAY PANEL

• US 20160190158A1
• Filed: 01/21/2015
• Published: 06/30/2016
• Est. Priority Date: 12/30/2014
• Status: Abandoned Application

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: SONG, Tao
• Application Number:
  US14/440,841
• Publication Number:
  US 20160190158A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/13456 Cell terminals located on one side of the display only
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

The disclosure provides an array substrate and a display panel. The array substrate comprises a display region and a non-display region surrounding the display region comprising a first non-display sub region at one side of the display region. An. integrated circuit chip is arranged in the first non-display sub region. The display region comprises data lines arranged along a first direction, first conductive lines comprising gate lines or common lines and arranged along a second direction, and second conductive lines. A first insulating layer having through holes is arranged between the first conductive lines and the second conductive lines. Each of the first conductive lines electrically connects to one end of the second conductive lines through corresponding through holes, and the other end of the second conductive lines and the data lines electrically connect to the integrated circuit chip. The array substrate has a narrower bezel.

Claims

1. An array substrate, comprising:

a display region; and

a non-display region surrounding the display region, comprising a first non-display sub region at one side of the display region, wherein an integrated circuit chip is arranged in the first non-display sub region;

wherein the display region comprises;

a plurality of data lines arranged along a first direction;

a plurality of first conductive lines arranged along a second direction, wherein the first conductive lines comprise gate lines or common lines;

a plurality of second conductive lines; and

a first insulating layer having a plurality of through holes arranged between the first conductive lines and the second conductive lines, wherein each of the first conductive lines electrically connects to one end of the second conductive lines through corresponding through holes, and the other end of the second conductive lines and the data lines electrically connect to the integrated circuit chip.

2. The array substrate according to claim 1, wherein at least one of the second conductive lines comprises a first portion and a second portion connected to the first portion;

the first portion is arranged along the first second direction, and is stacked on the first conductive lines.

3. The array substrate according to claim 2, wherein the second portion is arranged along the first direction and is stacked on the data lines.

4. The array substrate according to claim 1, wherein the first conductive lines, the first insulating layer and the second conductive lines are stacked in sequence;

the data lines are arranged on the second conductive lines through a second insulating layer, or the data lines are arranged on a surface of the second conductive lines away from the first insulating layer through a second insulating layer.

5. The array substrate according to claim 1, wherein the first non-display sub region is arranged corresponding to the bottom of the display region.

6. A display panel comprising an array substrate, wherein the array substrate comprises:

a display region; and

a non-display region surrounding the display region, comprising a first non-display sub region at one side of the display region, wherein an integrated circuit chip is arranged in the first non-display sub region;

wherein the display region comprises;

a plurality of data lines arranged along a first direction;

a plurality of first conductive lines arranged along a second direction, wherein the first conductive lines comprise gate lines or common lines;

a plurality of second conductive lines; and

a first insulating layer having a plurality of through holes arranged between the first conductive lines and the second conductive lines, wherein each of the first conductive lines electrically connects to one end of the second conductive lines through corresponding through holes, and the other end of the second conductive lines and the data lines electrically connect to the integrated circuit chip.

7. The display panel according to claim 6, wherein at least one of the second conductive lines comprises a first portion and a second portion connected to the first portion;

the first portion is arranged along the first second direction, and is stacked on the first conductive lines.

8. The display panel according to claim 7, wherein the second portion is arranged along the first direction and is stacked on the data lines.

9. The display panel according to claim 6, wherein the first conductive lines, the first insulating layer and the second conductive lines are stacked in sequence;

the data lines are arranged on the second conductive lines through a second insulating layer, or the data lines are arranged on a surface of the second conductive lines away from the first insulating layer through a second insulating layer.

10. The display panel according to claim 6, wherein the first non-display sub region is arranged corresponding to the bottom of the display region.