SEMICONDUCTOR DEVICE HAVING SOI SUBSTRATE

• US 20160190203A1
• Filed: 03/09/2016
• Published: 06/30/2016
• Est. Priority Date: 03/09/2010
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: ARAI, Yasuo, OKIHARA, Masao, KASAI, Hiroki
• Granted Patent: US 9,899,448 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/225 using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer H01L21/221 - H01L21/222 take precedence
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14658 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Claims

1. A semiconductor device, comprising:

an SOI substrate that includes a first surface and a second surface opposite to the first surface;

a semiconductor layer that includes a third surface opposite to the first surface and a fourth surface opposite to the third surface, the fourth surface having a semiconductor element disposed thereon;

an oxide film layer that is formed in contact with the first surface and the third surface;

a first diffusion layer that is formed in a first region including the semiconductor layer in planar view, that is formed on a surface opposite to the third surface via the oxide film layer and that is connected to a reference potential;

a second diffusion layer that is connected to the reference potential and that is formed in a part of a region of the first surface corresponding to a second region that is adjacent to the first region in planar view;

a third diffusion layer that is formed in a part of a region of the first surface corresponding to the second region and that is formed separately from the second diffusion layer; and

a voltage application unit that applies a voltage to the second surface and the third diffusion layer in order to deplete the SOI substrate.

2. The semiconductor device according to claim 1, wherein:

the SOI substrate and the third diffusion layer are first conductivity types;

the second diffusion layer is a second conductivity type that is opposite in conductivity type to the first conductivity type; and

the second diffusion layer and the third diffusion layer form a diode.

3. The semiconductor device according to claim 2, wherein the diode is a photo diode.

4. The semiconductor device according to claim 1, further comprising:

a first electrode that passes through the oxide film layer and is connected to the first diffusion layer;

a second electrode that passes through the oxide film layer and is connected to the second diffusion layer; and

a third electrode that passes through the oxide film layer and is connected to the third diffusion layer, wherein;

the first diffusion layer is connected to the reference potential via the first electrode;

the second diffusion layer is connected to the reference potential via the second electrode; and

the third diffusion layer is connected to the voltage application unit via the third electrode.