SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

• US 20160190268A1
• Filed: 12/29/2014
• Published: 06/30/2016
• Est. Priority Date: 12/29/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YANG, Tsung-Hsueh, WU, Chang-Ming, MIN, Chung-Chiang, LIU, Shih-Chang
• Granted Patent: US 9,673,204 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure also includes a first isolation structure partially embedded in the substrate. The first isolation structure has a first upper surface with a first recess. The semiconductor device structure further includes a second isolation structure partially embedded in the substrate. In addition, the semiconductor device structure includes a first gate over the substrate and between the first isolation structure and the second isolation structure. The first gate extends onto the first upper surface to cover the first recess. The semiconductor device structure includes a second gate over the first gate.

Claims

1. A semiconductor device structure, comprising:

a substrate;

a first isolation structure partially embedded in the substrate, wherein the first isolation structure has a first upper surface with a first recess extending below a top of the first isolation structure;

a second isolation structure partially embedded in the substrate;

a first gate over the substrate and between the first isolation structure and the second isolation structure, wherein the first gate extends onto the first upper surface and above the top of the first isolation structure to cover the first recess; and

a second gate over the first gate.

2. The semiconductor device structure as claimed in claim 1, wherein the second isolation structure has a second upper surface with a second recess, and the first gate further extends onto the second upper surface to cover the second recess.

3. The semiconductor device structure as claimed in claim 1, wherein the first recess is adjacent to a first edge of the first isolation structure.

4. The semiconductor device structure as claimed in claim 1, wherein the first gate has a width greater than a distance between the first isolation structure and the second isolation structure.

5. The semiconductor device structure as claimed in claim 1, further comprising:

a dielectric layer between the first gate and the second gate, wherein the dielectric layer has a bottom surface in contact with the top of the first isolation structure, and the bottom surface of the dielectric layer is lower than a top of the first gate that extends onto the first upper surface.

6. The semiconductor device structure as claimed in claim 1, wherein the second gate covers a third upper surface and a sidewall of the first gate.

7. The semiconductor device structure as claimed in claim 1, wherein the first gate is in a T-like shape.

8. The semiconductor device structure as claimed in claim 1, wherein the first isolation structure has a first protruding edge extending away from the substrate.

9. The semiconductor device structure as claimed in claim 8, wherein the second isolation structure has a second protruding edge extending away from the substrate, and the first gate covers the first protruding edge and the second protruding edge.

21. The semiconductor device structure as claimed in claim 1, wherein the first gate has a lower portion and an upper portion over the lower portion, a top of the upper portion of the first gate is above the top of the first isolation structure, and a first width of the upper portion is greater than a second width of the lower portion.

22. The semiconductor device structure as claimed in claim 21, wherein the first gate further has a neck portion between the lower portion and the upper portion, and the second width of the lower portion is greater than a third width of the neck portion.

23. The semiconductor device structure as claimed in claim 21, wherein a ratio of the first width of the upper portion to the second width of the lower portion ranges from about 1.05 to about 1.4.

24. The semiconductor device structure as claimed in claim 22, wherein a ratio of the first width of the upper portion to the third width of the neck portion ranges from about 1.25 to about 2.

25. The semiconductor device structure as claimed in claim 8, wherein the second isolation structure has a second protruding edge extending away from the substrate.

10. A semiconductor device structure, comprising:

a substrate;

a first isolation structure partially embedded in the substrate, wherein the first isolation structure has a first upper surface;

a second isolation structure partially embedded in the substrate, wherein the second isolation structure has a second upper surface;

a first gate over the substrate and between the first isolation structure and the second isolation structure, wherein the first gate extends onto the first upper surface and above a toy of the first isolation structure and extends onto the second upper surface, the first gate has a lower portion and an upper portion over the lower portion, and a first width of the upper portion is greater than a second width of the lower portion; and

a second gate over the first gate.

11. The semiconductor device structure as claimed in claim 10, wherein the first isolation structure has a first protruding edge extending away from the substrate and into the first gate, and the second isolation structure has a second protruding edge extending away from the substrate and into the first gate.

14. The semiconductor device structure as claimed in claim 11, wherein the first gate has a third protruding edge and a fourth protruding edge extending toward the substrate.

15. The semiconductor device structure as claimed in claim 14, wherein the third protruding edge is over the first protruding edge, and the fourth protruding edge is over the second protruding edge.

12. A semiconductor device structure, comprising:

a substrate;

a first isolation structure partially embedded in the substrate, wherein the first isolation structure has a first upper surface;

a second isolation structure partially embedded in the substrate, wherein the second isolation structure has a second upper surface;

a first gate over the substrate and between the first isolation structure and the second isolation structure, wherein the first gate extends onto the first upper surface and the second upper surface, the first gate has a lower portion and an upper portion over the lower portion, and a first width of the upper portion is greater than a second width of the lower portion; and

a second gate over the first gate,

wherein the first isolation structure has a first protruding edge extending away from the substrate and into the first gate, and the second isolation structure has a second protruding edge extending away from the substrate and into the first gate, and

wherein the first gate further has a neck portion between the lower portion and the upper portion, and the second width of the lower portion is greater than a third width of the neck portion.

13. The semiconductor device structure as claimed in claim 12, wherein the neck portion is between the first protruding edge and the second protruding edge.

16-20. -20. (canceled)