INTEGRATED CIRCUIT COMPRISING PMOS TRANSISTORS WITH DIFFERENT VOLTAGE THRESHOLDS

• US 20160197018A1
• Filed: 12/22/2015
• Published: 07/07/2016
• Est. Priority Date: 12/22/2014
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation), International Business Machines Corporation
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation), International Business Machines Corporation
• Inventors: ANDRIEU, Francois, DEGORS, Nicolas, PERREAU, Pierre
• Granted Patent: US 9,520,330 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

There is provided a method for the manufacture of an integrated circuit, including a substrate and an insulating layer formed on the substrate; a first pMOS transistor formed on the insulating layer and including a channel formed in a first layer of a silicon-germanium alloy, having a first thickness and first average germanium density; a gate oxide layer having a first equivalent oxide thickness; a second pMOS transistor formed on the insulating layer and further including a channel formed in a second layer of a silicon-germanium alloy, having a second thickness which is greater than the first and a second average germanium density which is lower than the first; and a gate oxide layer having a second equivalent oxide thickness which is greater than the first.

Claims

1. A method for the manufacture of an integrated circuit incorporating first and second pMOS transistors, comprising:

providing a substrate, an insulating layer formed on the substrate, and a silicon layer formed on at least first and second zones of the insulating layer;

reducing a thickness of the silicon layer above the first zone of the insulating layer, such that the silicon layer in the first zone shows a smaller thickness than the silicon layer in the second zone;

forming a first deposit of silicon-germanium on the silicon layer above the first zone of the insulating layer and a second deposit of silicon-germanium on the silicon layer above the second zone of the insulating layer;

forming a mask covering the second deposit of silicon-germanium and exposing the first deposit of silicon-germanium;

in the presence of said mask, condensing germanium in the first deposit to form silicon oxide on the surface of the first deposit, such that germanium is diffused into said silicon layer below the first deposit to form a layer of silicon-germanium between said silicon oxide and said first zone of the insulating layer;

removing said formed silicon oxide, until the first thickness of the formed layer of silicon-germanium is smaller than the second cumulative thickness of the second deposit of silicon-germanium and the silicon layer above the second zone of the insulating layer, such that the average density of germanium in the thickness of the silicon-germanium layer formed from the second deposit is greater than the average density of germanium in the cumulative thickness of the second deposit of silicon-germanium and the silicon layer above the second zone;

removing said formed mask; and

forming, on said silicon-germanium layer, a first gate stack of the first pMOS transistor, said first gate stack incorporating a first gate oxide and forming, on said second deposit formed on the silicon layer, a second gate stack of the second pMOS transistor, said second stack incorporating a second gate oxide, wherein the second gate oxide has a second equivalent oxide thickness, which is greater than a first equivalent oxide thickness of the first gate oxide.

2. The method for the manufacture of an integrated circuit according to claim 1, wherein the formation of said first and second deposits of silicon-germanium includes the epitaxial growth of silicon-germanium.

3. The method for the manufacture of an integrated circuit according to claim 1, further comprising forming first and second ground planes respectively below the first and second zones of the insulating layer, wherein said forming includes the incorporation of dopants into the substrate.

4. The method for the manufacture of an integrated circuit according to claim 1, wherein the forming said mask comprises a depositing a nitride to a minimum thickness of 10 nm.

5. The method for the manufacture of an integrated circuit according to claim 1, wherein the removal of silicon oxide is executed such that said formed silicon-germanium layer incorporates at least 90% of the germanium dosing from the first deposit of germanium.

6. The method for the manufacture of an integrated circuit according to claim 1, wherein said first and second deposits of silicon-germanium are formed simultaneously, and are of equal thickness, with an equal surface dosing of silicon-germanium.

7. The method for the manufacture of an integrated circuit according to claim 1, wherein said layer of silicon-germanium and said second deposit of silicon-germanium show respective thicknesses that are smaller than their respective relaxation thicknesses.

8. The method for the manufacture of an integrated circuit according to claim 1, wherein 1.2*Ct4<

Ct3, where Ct4 is said first thickness and Ct3 is said second thickness.

9. The method for the manufacture of an integrated circuit according to claim 8, wherein Ct3 ranges from 7 nm to 20 nm and Ct4 ranges from 5 nm to 8 nm.

10. The method for the manufacture of an integrated circuit according to claim 1, wherein 1.5*Gt4<

Gt3, where Gt4 is said first equivalent oxide thickness and Gt3 is said second equivalent oxide thickness.

11. The method for the manufacture of an integrated circuit according to claim 1, wherein said substrate provided is of the SOI type, and wherein the channels of the first and second pMOS transistors formed are of the fully-depleted type.