METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• US 20160197066A1
• Filed: 10/30/2015
• Published: 07/07/2016
• Est. Priority Date: 01/05/2015
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kuramoto, Takafumi, Uchida, Shinichi, Koh, Risho
• Granted Patent: US 9,558,967 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31058 of organic layers
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92147 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/564 : Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 23/58 : Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 25/074 : Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

An improvement is achieved in the reliability of a semiconductor device by preventing a dielectric breakdown between two semiconductor chips facing each other. During the manufacturing of first and second semiconductor chips, the process of planarizing the upper surfaces of insulating films is performed. Then, the first and second semiconductor chips are stacked via an insulating sheet with the respective insulating films of the first and second semiconductor chips facing each other such that the respective coils of the first and second semiconductor chips are magnetically coupled to each other.

Claims

1. A method of manufacturing a semiconductor device including a first semiconductor chip having a first coil, a second semiconductor chip having a second coil, and an insulating sheet interposed between the first and second semiconductor chips, the first and second semiconductor chips being stacked via the insulating sheet, and the first and second coils being magnetically coupled to each other, the method comprising the steps of:

(a) providing the first semiconductor chip;

(b) providing the second semiconductor chip; and

(c) stacking the first and second semiconductor chips via the insulating sheet so as to magnetically couple the first and second coils to each other;

wherein the step (a) includes the steps of;

(a1) forming a first wiring structure having one or more wiring layers and including the first coil over a first semiconductor substrate;

(a2) forming a first insulating film over the first wiring structure; and

(a3) planarizing an upper surface of the first insulating film,

wherein the step (b) includes the steps of;

(b1) forming a second wiring structure having one or more wiring layers and including the second coil over a second semiconductor substrate;

(b2) forming a second insulating film over the second wiring structure; and

(b3) planarizing an upper surface of the second insulating film, and

wherein, in the step (c), the first and second semiconductor chips are stacked via the insulating sheet with the first insulating film of the first semiconductor chip and the second insulating film of the second semiconductor chip facing each other.

2. The method of manufacturing the semiconductor device according to claim 1,

wherein the step (a3) includes the steps of:

(a4) forming a first mask layer over the first insulating film; and

(a5) etching back the first insulating film using the first mask layer as an etching mask, and

wherein the step (b3) includes the steps of;

(b4) forming a second mask layer over the second insulating film; and

(b5) etching the second insulating film using the second mask layer as an etching mask.

3. The method of manufacturing the semiconductor device according to claim 2,

wherein, by performing the step (a5), a planarity of the upper surface of the first insulating film is improved, and

wherein, by performing the step (b5), a planarity of the upper surface of the second insulating film is improved.

4. The method of manufacturing the semiconductor device according to claim 2,

wherein the first insulating film includes a first resin film,

wherein, in the step (a5), the first resin film is etched back,

wherein the second insulating film includes a second resin film, and

wherein, in the step (b5), the second resin film is etched back.

5. The method of manufacturing the semiconductor device according to claim 4,

wherein each of the first and second resin films is made of polyimide.

6. The method of manufacturing the semiconductor device according to claim 1,

wherein, in the step (a3), the upper surface of the first insulating film is polished to be planarized, and

wherein, in the step (b3), the upper surface of the second insulating film is polished to be planarized.

7. The method of manufacturing the semiconductor device according to claim 6,

wherein, in the step (a3), the upper surface of the first insulating film is polished by a CMP method, and

wherein, in the step (b3), the upper surface of the second insulating film is polished by a CMP method.

8. The method of manufacturing the semiconductor device according to claim 6,

wherein the first insulating film includes a first silicon dioxide film,

wherein, in the step (a3), the first silicon dioxide film is polished,

wherein the second insulating film includes a second silicon dioxide film, and

wherein, in the step (b3), the second silicon dioxide film is polished.

9. The method of manufacturing the semiconductor device according to claim 1,

wherein the first insulating film is a film in an uppermost layer of the first semiconductor chip, and

wherein the second insulating film is a film in an uppermost layer of the second semiconductor chip.

10. The method of manufacturing the semiconductor device according to claim 1,

wherein the step (c) includes the steps of:

(c1) mounting the first semiconductor chip over a chip mounting portion; and

(c2) mounting the second semiconductor chip over the first semiconductor chip via the insulating sheet to stack the second semiconductor chip over the first semiconductor chip with the first insulating film of the first semiconductor chip and the second insulating film of the second semiconductor chip facing each other.

11. The method of manufacturing the semiconductor device according to claim 10,

wherein the first semiconductor chip has a plurality of first pads,

wherein the second semiconductor chip has a plurality of second pads,

the method further comprising the step of:

(d) after the step (c), electrically coupling a plurality of first external terminals to the first pads of the first semiconductor chip via a plurality of first conductive coupling members and electrically coupling a plurality of second external terminals to the second pads of the second semiconductor chip via a plurality of second conductive coupling members.

12. The method of manufacturing the semiconductor device according to claim 11, further comprising the step of:

(e) after the step (d), forming a sealing portion which seals the first semiconductor chip, the second semiconductor chip, the insulating sheet, the chip mounting portion, the first conductive coupling members, the second conductive coupling members, the first external terminals, and the second external terminals.